// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// positSqrt.v
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// positSqrt.v
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// - posit number square root function
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// - posit number square root function
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// - parameterized width
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// - parameterized width
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//
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//
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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// This function currently only seems to work with even sizes of
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// exponents.
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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`include "positConfig.sv"
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module positSqrt(clk, ce, i, o, start, done, zero, inf);
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module positSqrt(clk, ce, i, o, start, done, zero, inf);
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`include "positSize.sv"
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1)-1;
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localparam rs = $clog2(PSTWID-1)-1;
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input clk;
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input clk;
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input ce;
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input ce;
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output reg [PSTWID-1:0] o;
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output reg [PSTWID-1:0] o;
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input start;
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input start;
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output done;
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output done;
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output zero;
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output zero;
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output inf;
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output inf;
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wire si, so;
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wire si, so;
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wire [rs:0] rgmi;
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wire [rs:0] rgmi;
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wire rgsi;
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wire rgsi;
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wire [es-1:0] expi;
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wire [es-1:0] expi;
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wire [PSTWID-es-1:0] sigi;
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wire [PSTWID-es-1:0] sigi;
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wire zeri;
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wire zeri;
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wire infi;
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wire infi;
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wire inf = infi;
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wire inf = infi;
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wire zero = zeri;
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wire zero = zeri;
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positDecompose #(PSTWID,es) u1 (
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positDecompose #(PSTWID,es) u1 (
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.i(i),
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.i(i),
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.sgn(si),
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.sgn(si),
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.rgs(rgsi),
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.rgs(rgsi),
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.rgm(rgmi),
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.rgm(rgmi),
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.exp(expi),
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.exp(expi),
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.sig(sigi),
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.sig(sigi),
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.zer(zeri),
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.zer(zeri),
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.inf(infi)
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.inf(infi)
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);
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);
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assign so = si; // square root of positive numbers only
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assign so = si; // square root of positive numbers only
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// Compute length of significand. This length is needed to align the
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// significand input to the square root module.
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//wire [rs+1:0] rgml1 = rgsi ? rgmi + 2'd2 : rgmi + 2'd1;
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//wire [rs+1:0] sigl = PSTWID-rgml1-es-1;
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// The length could be zero or less
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//wire [rs:0] sigl1 = sigl[rs+1] ? {rs{1'b0}} : sigl;
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// Compute exponent
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wire [rs+1:0] rgm1 = rgsi ? rgmi : -rgmi;
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wire [rs+1:0] rgm1 = rgsi ? rgmi : -rgmi;
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wire [rs+es+1:0] rx1 = {rgm1,expi};
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wire [rs+es+1:0] rx1 = {rgm1,expi};
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// If exponent is odd, make it even. May need to shift the significand later.
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// If exponent is odd, make it even. May need to shift the significand later.
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wire [rs+es+1:0] rxtmp = {{2{rx1[rs+es+1]}},rx1} >> 1; // right shift takes square root of exponent
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wire [rs+es+1:0] rxtmp = {{2{rx1[rs+es+1]}},rx1} >> 1; // right shift takes square root of exponent
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assign sqrinf = infi;
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assign sqrinf = infi;
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assign sqrneg = so;
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assign sqrneg = so;
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// If the exponent was made even, shift the significand left.
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// If the exponent was made even, shift the significand left.
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wire [PSTWID-1:0] sig1 = rx1[0] ? {sigi,1'b0} : {1'b0,sigi};
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wire [PSTWID-1:0] sig1 = (rx1[0] ^ ~es[0]) ? {sigi,1'b0} : {1'b0,sigi};
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wire ldd;
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wire ldd;
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(start), .o(ldd));
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(start), .o(ldd));
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wire [PSTWID*3-1:0] sqrto;
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wire [PSTWID*3-1:0] sqrto;
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wire [rs:0] lzcnt;
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wire [rs:0] lzcnt;
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// iqsrt2 left aligns the number
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// iqsrt2 left aligns the number
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isqrt2 #(PSTWID*3/2) u2
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isqrt2 #(PSTWID*3/2) u2
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ce(ce),
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.ce(ce),
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.ld(ldd),
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.ld(ldd),
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.a({sig1,{(PSTWID/2+1-(PSTWID%2)){1'b0}}}),
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// Align the input according to odd/even length
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.a({sig1,{PSTWID/2{1'b0}}}),
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.o(sqrto),
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.o(sqrto),
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.done(done),
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.done(done),
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.lzcnt(lzcnt)
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.lzcnt(lzcnt)
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);
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);
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// There should not be very many leading zeros in the number as the number is
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// There should not be very many leading zeros in the number as the number is
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// always between 1 and 2, so the square root is between 1.0 and 1.414....
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// always between 1 and 2, so the square root is between 1.0 and 1.414....
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// May want to change the leading zero detect to be a little more efficient.
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// May want to change the leading zero detect to be a little more efficient.
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//positCntlz #(.PSTWID(PSTWID)) u4 (.i(sqrto[PSTWID-1:0]), .o(lzcnt));
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//positCntlz #(.PSTWID(PSTWID)) u4 (.i(sqrto[PSTWID-1:0]), .o(lzcnt));
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wire [PSTWID*2-1:0] sqrt1 = sqrto[PSTWID*3-1:PSTWID];// << (lzcnt + PSTWID/2);
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wire [PSTWID*2-1:0] sqrt1 = sqrto[PSTWID*3-1:PSTWID];// << (lzcnt + PSTWID/2);
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// Make a negative rx positive
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// Make a negative rx positive
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wire [rs+es+1:0] rxtmp2c = rxtmp[rs+es+1] ? ~rxtmp + 2'd1 : rxtmp;
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wire [rs+es+1:0] rxtmp2c = rxtmp[rs+es+1] ? ~rxtmp + 2'd1 : rxtmp;
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// Break out the exponent and regime portions
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// Break out the exponent and regime portions
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wire [es-1:0] exp = rxtmp[es-1:0];
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wire [es-1:0] exp = rxtmp[es-1:0];
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// Take absolute value of regime portion
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// Take absolute value of regime portion
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wire srxtmp = rxtmp[rs+es+1];
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wire srxtmp = rxtmp[rs+es+1];
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wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
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wire [rs:0] rgm = srxtmp ? -rxtmp[rs+es+1:es] : rxtmp[rs+es+1:es];
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// Compute the length of the regime bit string, +1 for positive regime
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// Compute the length of the regime bit string, +1 for positive regime
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wire [rs:0] rgml = srxtmp ? rxtmp2c[rs+es:es] + 2'd1: rxtmp2c[rs+es:es] + 2'd2;
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wire [rs:0] rgml = srxtmp ? rxtmp2c[rs+es:es] + 2'd1: rxtmp2c[rs+es:es] + 2'd2;
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// Build expanded posit number:
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// Build expanded posit number:
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// trim one leading bit off the product bits
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// trim one leading bit off the product bits
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// and keep guard, round bits, and create sticky bit
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// and keep guard, round bits, and create sticky bit
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wire [PSTWID*3-1+9-es:0] tmp;
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wire [PSTWID*3-1+9-es:0] tmp;
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generate begin : gTmp
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generate begin : gTmp
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case(es)
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case(es)
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0: assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,sqrt1[PSTWID*2-2:0],{9-es{1'b0}}};
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0: assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,sqrt1[PSTWID*2-2:0],{9-es{1'b0}}};
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1,2,3,4,5,6:
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1,2,3,4,5,6:
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assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,exp,sqrt1[PSTWID*2-2:0],{9-es{1'b0}}};
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assign tmp = {{PSTWID-1{~srxtmp}},srxtmp,exp,sqrt1[PSTWID*2-2:0],{9-es{1'b0}}};
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default:
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default:
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always @*
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always @*
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begin
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begin
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$display("positSqrt: unsupported es");
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$display("positSqrt: unsupported es");
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$finish;
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$finish;
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end
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end
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endcase
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endcase
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end
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end
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endgenerate
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endgenerate
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wire [PSTWID*3-1+9-es:0] tmp1 = tmp >> rgml;
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wire [PSTWID*3-1+9-es:0] tmp1 = tmp >> rgml;
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// Rounding
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// Rounding
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// Guard, Round, and Sticky
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// Guard, Round, and Sticky
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wire L = tmp1[PSTWID+8], G = tmp1[PSTWID+7], R = tmp1[PSTWID+6], St = |tmp1[PSTWID+5:0],
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wire L = tmp1[PSTWID+8], G = tmp1[PSTWID+7], R = tmp1[PSTWID+6], St = |tmp1[PSTWID+5:0],
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ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID+7:PSTWID+8] + rnd_ulp;
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID+7:PSTWID+8] + rnd_ulp;
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wire [PSTWID-1:0] tmp1_rnd = (rgml < PSTWID-es-2) ? tmp1_rnd_ulp[PSTWID-1:0] : tmp1[2*PSTWID+7:PSTWID+8];
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wire [PSTWID-1:0] tmp1_rnd = (rgml < PSTWID-es-2) ? tmp1_rnd_ulp[PSTWID-1:0] : tmp1[2*PSTWID+7:PSTWID+8];
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always @*
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always @*
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casez({infi,sqrinf,sqrneg,zero})
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casez({infi,sqrinf,sqrneg,zero})
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4'b1???: o = {1'b1,{PSTWID-1{1'b0}}};
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4'b1???: o = {1'b1,{PSTWID-1{1'b0}}};
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4'b01??: o = {1'b1,{PSTWID-1{1'b0}}};
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4'b01??: o = {1'b1,{PSTWID-1{1'b0}}};
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4'b001?: o = {1'b1,{PSTWID-1{1'b0}}};
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4'b001?: o = {1'b1,{PSTWID-1{1'b0}}};
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4'b0001: o = {PSTWID{1'b0}};
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4'b0001: o = {PSTWID{1'b0}};
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default: o = {1'b0,tmp1_rnd[PSTWID-1:1]};
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default: o = {1'b0,tmp1_rnd[PSTWID-1:1]};
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endcase
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endcase
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endmodule
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endmodule
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