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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [DivGoldschmidt.v] - Diff between revs 14 and 26

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`timescale 1ns / 1ps
`timescale 1ns / 1ps
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//
//
//      DivGoldschmidt.v
//      DivGoldschmidt.v
//              
//              
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
// (at your option) any later version.                                      
//                                                                          
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
// GNU General Public License for more details.                             
//                                                                          
//                                                                          
// You should have received a copy of the GNU General Public License        
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//                                                                          
//
//
// ============================================================================
// ============================================================================
//
//
module DivGoldschmidt(rst, clk, ld, a, b, q, f0, done, lzcnt);
module DivGoldschmidt(rst, clk, ld, a, b, q, done, lzcnt);
parameter WID=32;
parameter WID=32;
parameter WHOLE=16;
parameter WHOLE=16;
parameter POINTS=16;
parameter POINTS=16;
parameter LEFT=1'b1;
parameter LEFT=1'b1;
localparam SIZE=WID+WHOLE;
localparam SIZE=WID+WHOLE;
localparam POINTS2 = POINTS+WHOLE;
localparam POINTS2 = POINTS+WHOLE;
input rst;
input rst;
input clk;
input clk;
input ld;
input ld;
input [WID-1:0] a;
input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] b;
output reg [WID*2-1:0] q;
output reg [WID*2-1:0] q;
output reg [SIZE-1:0] f0;
 
output reg done;
output reg done;
output reg [7:0] lzcnt;
output reg [7:0] lzcnt;
parameter IDLE = 2'd0;
parameter IDLE = 2'd0;
parameter DIV = 2'd1;
parameter DIV = 2'd1;
parameter DONE = 2'd2;
parameter DONE = 2'd2;
parameter DIV2 = 2'd3;
parameter DIV2 = 2'd3;
 
 
integer n;
integer n;
// Scale D so it is between 0 < D < 1 (shift)
// Scale D so it is between 0 < D < 1 (shift)
reg [SIZE-1:0] F;
reg [SIZE-1:0] F;
reg [SIZE*3-1:0] N, D;
reg [SIZE*3-1:0] N, D;
wire [SIZE*3-1:0] N1, D1;
wire [SIZE*3-1:0] N1, D1;
assign N1 = N * F;
assign N1 = N * F;
assign D1 = D * F;
assign D1 = D * F;
reg [1:0] state = IDLE;
reg [1:0] state = IDLE;
reg [7:0] count = 0;
reg [7:0] count = 0;
reg [7:0] lzcnt2;
reg [7:0] lzcnt2;
wire [7:0] shft;
wire [7:0] shft;
 
 
// Count the leading zeros on the b side input. Determines how much
// Count the leading zeros on the b side input. Determines how much
// shifting is required.
// shifting is required.
always @*
always @*
begin
begin
        lzcnt2 = 8'd0;
        lzcnt2 = 8'd0;
        if (b[WID-1]==1'b0)
        if (b[WID-1]==1'b0)
                for (n = WID-2; n >= 0; n = n - 1)
                for (n = WID-2; n >= 0; n = n - 1)
                        if(b[n] && lzcnt2==8'd0)
                        if(b[n] && lzcnt2==8'd0)
                                lzcnt2 = (WID-1)-n;
                                lzcnt2 = (WID-1)-n;
end
end
 
 
 
 
// Count the leading zeros in the output. the float divider uses this.
// Count the leading zeros in the output. the float divider uses this.
always @*
always @*
begin
begin
        lzcnt = 8'd0;
        lzcnt = 8'd0;
        if (q[WID*2-1]==1'b0)
        if (q[WID*2-1]==1'b0)
                for (n = WID*2-2; n >= 0; n = n - 1)
                for (n = WID*2-2; n >= 0; n = n - 1)
                        if(q[n] && lzcnt==8'd0)
                        if(q[n] && lzcnt==8'd0)
                                lzcnt = (WID*2-1)-n;
                                lzcnt = (WID*2-1)-n;
end
end
 
 
wire shift_left = lzcnt2 > WHOLE;
wire shift_left = lzcnt2 > WHOLE;
assign shft = shift_left ? lzcnt2-WHOLE : WHOLE-lzcnt2;
assign shft = shift_left ? lzcnt2-WHOLE : WHOLE-lzcnt2;
//assign done = (state==IDLE && !ld)||state==DONE;
//assign done = (state==IDLE && !ld)||state==DONE;
 
 
always @(posedge clk)
always @(posedge clk)
if (rst) begin
if (rst) begin
        done <= 1'b0;
        done <= 1'b0;
        count <= 6'd0;
        count <= 6'd0;
        state <= IDLE;
        state <= IDLE;
end
end
else begin
else begin
        done <= 1'b0;
        done <= 1'b0;
case(state)
case(state)
IDLE:
IDLE:
        begin
        begin
                if (ld) begin
                if (ld) begin
                        // Shifting the numerator and denomintor right or left using a barrel
                        // Shifting the numerator and denomintor right or left using a barrel
                        // or funnel shifter is what gives Goldschmidt a lot of it's performance.
                        // or funnel shifter is what gives Goldschmidt a lot of it's performance.
                        // Most of the divide is being performed by shifting.
                        // Most of the divide is being performed by shifting.
                        // For most floating point numbers shifting left isn't required as the
                        // For most floating point numbers shifting left isn't required as the
                        // number is always between 1.0 and 2.0. Instead typically only a single
                        // number is always between 1.0 and 2.0. Instead typically only a single
                        // shift to the right is required. For fixed point numbers however, we
                        // shift to the right is required. For fixed point numbers however, we
                        // probably want to be able to shift left, hence the LEFT parameter.
                        // probably want to be able to shift left, hence the LEFT parameter.
                        // With no left shifting the only impact is for denormal numbers which
                        // With no left shifting the only impact is for denormal numbers which
                        // take longer for the divide to converge.
                        // take longer for the divide to converge.
                        if (shift_left) begin
                        if (shift_left) begin
                                if (LEFT) begin
                                if (LEFT) begin
                                        N <= {16'd0,a,{WHOLE{1'b0}}} << shft;
                                        N <= {16'd0,a,{WHOLE{1'b0}}} << shft;
                                        D <= {16'd0,b,{WHOLE{1'd0}}} << shft;
                                        D <= {16'd0,b,{WHOLE{1'd0}}} << shft;
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
                                        f0 <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
 
                                end
                                end
                                else begin
                                else begin
                                        N <= {16'd0,a,{WHOLE{1'b0}}};
                                        N <= {16'd0,a,{WHOLE{1'b0}}};
                                        D <= {16'd0,b,{WHOLE{1'd0}}};
                                        D <= {16'd0,b,{WHOLE{1'd0}}};
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
                                        f0 <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
 
                                end
                                end
                        end
                        end
                        else begin
                        else begin
                                N <= {16'd0,a,{WHOLE{1'b0}}} >> shft;
                                N <= {16'd0,a,{WHOLE{1'b0}}} >> shft;
                                D <= {16'd0,b,{WHOLE{1'd0}}} >> shft;
                                D <= {16'd0,b,{WHOLE{1'd0}}} >> shft;
                                F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
                                F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
                                f0 <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
 
                        end
                        end
                        count <= 0;
                        count <= 0;
                        state <= DIV;
                        state <= DIV;
                end
                end
        end
        end
DIV:
DIV:
        begin
        begin
                $display("C: %d N: %x D: %x F: %x", count, N,D,F);
                $display("C: %d N: %x D: %x F: %x", count, N,D,F);
                N <= N1[SIZE*3-1:POINTS2] + N1[POINTS2-1];
                N <= N1[SIZE*3-1:POINTS2] + N1[POINTS2-1];
                D <= D1[SIZE*3-1:POINTS2] + D1[POINTS2-1];
                D <= D1[SIZE*3-1:POINTS2] + D1[POINTS2-1];
                F <= {16'd2,{POINTS2{1'd0}}} - (D1[SIZE*3-1:POINTS2] + D1[POINTS2-1]);
                F <= {16'd2,{POINTS2{1'd0}}} - (D1[SIZE*3-1:POINTS2] + D1[POINTS2-1]);
//              q <= N1[SIZE*2-1:POINTS2] + N1[POINTS2-1];
//              q <= N1[SIZE*2-1:POINTS2] + N1[POINTS2-1];
                if (D[SIZE*3-1:0]=={2'h1,{POINTS2{1'd0}}})
                if (D[SIZE*3-1:0]=={2'h1,{POINTS2{1'd0}}})
                        state <= DONE;
                        state <= DONE;
                count <= count + 1;
                count <= count + 1;
        end
        end
DONE:
DONE:
        begin
        begin
                done <= 1'b1;
                done <= 1'b1;
                q <= N[SIZE*3-1:0];
                q <= N[SIZE*3-1:0];
                state <= IDLE;
                state <= IDLE;
        end
        end
endcase
endcase
end
end
 
 
endmodule
endmodule
 
 
module G_divider_tb();
module G_divider_tb();
parameter WID=4;
parameter WID=4;
reg rst;
reg rst;
reg clk;
reg clk;
reg ld;
reg ld;
wire done;
wire done;
wire [WID*2-1:0] qo;
wire [WID*2-1:0] qo;
wire [7:0] f0;
 
reg [3:0] state;
reg [3:0] state;
reg [3:0] a, b;
reg [3:0] a, b;
reg [7:0] count;
reg [7:0] count;
 
 
initial begin
initial begin
        clk = 1;
        clk = 1;
        rst = 0;
        rst = 0;
        #100 rst = 1;
        #100 rst = 1;
        #100 rst = 0;
        #100 rst = 0;
        #100 ld = 1;
        #100 ld = 1;
        #150 ld = 0;
        #150 ld = 0;
end
end
 
 
always #10 clk = ~clk;  //  50 MHz
always #10 clk = ~clk;  //  50 MHz
 
 
always @(posedge clk)
always @(posedge clk)
if (rst) begin
if (rst) begin
        state <= 3'd0;
        state <= 3'd0;
        count = 0;
        count = 0;
end
end
else begin
else begin
case(state)
case(state)
3'd0:
3'd0:
        begin
        begin
                ld <= 1;
                ld <= 1;
                a <= count[7:4];
                a <= count[7:4];
                b <= count[3:0];
                b <= count[3:0];
        end
        end
3'd1:
3'd1:
        if (done) begin
        if (done) begin
                $display("C: %x Q: %x  f: %x", count, qo, f0);
                $display("C: %x Q: %x  f: %x", count, qo, f0);
                state <= 3'd2;
                state <= 3'd2;
        end
        end
3'd2:
3'd2:
        begin
        begin
                count <= count + 8'd1;
                count <= count + 8'd1;
                state <= 3'd0;
                state <= 3'd0;
        end
        end
endcase
endcase
end
end
 
 
DivGoldschmidt #(.WID(WID),.WHOLE(1),.POINTS(3)) u00
DivGoldschmidt #(.WID(WID),.WHOLE(1),.POINTS(3)) u00
(
(
        .rst(rst),
        .rst(rst),
        .clk(clk),
        .clk(clk),
        .ld(ld),
        .ld(ld),
//      .sgn(1'b1),
//      .sgn(1'b1),
//      .isDivi(1'b0),
//      .isDivi(1'b0),
        .a(a),
        .a(a),
        .b(b),
        .b(b),
//      .imm(64'd123),
//      .imm(64'd123),
        .q(qo),
        .q(qo),
        .f0(f0),
 
//      .ro(ro),
//      .ro(ro),
//      .dvByZr(),
//      .dvByZr(),
        .left_right(),
        .done(done),
        .shift(),
        .lzcnt()
        .done(done)
 
);
);
 
 
endmodule
endmodule
 
 
 
 

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