`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpAddsub.v
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// fpAddsub.v
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// - floating point adder/subtracter
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// - floating point adder/subtracter
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// - two cycle latency
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// - two cycle latency
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// - can issue every clock cycle
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// - can issue every clock cycle
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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module fpAddsub(clk, ce, rm, op, a, b, o);
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module fpAddsub(clk, ce, rm, op, a, b, o);
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parameter WID = 128;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk; // system clock
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input clk; // system clock
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input ce; // core clock enable
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input ce; // core clock enable
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input op; // operation 0 = add, 1 = subtract
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input op; // operation 0 = add, 1 = subtract
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input [WID-1:0] a; // operand a
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input [WID-1:0] a; // operand a
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input [WID-1:0] b; // operand b
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input [WID-1:0] b; // operand b
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output [EX:0] o; // output
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output [EX:0] o; // output
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// variables
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// variables
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wire so; // sign output
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wire so; // sign output
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wire [EMSB:0] xo; // de normalized exponent output
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wire [EMSB:0] xo; // de normalized exponent output
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reg [EMSB:0] xo1; // de normalized exponent output
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reg [EMSB:0] xo1; // de normalized exponent output
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wire [FX:0] mo; // mantissa output
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wire [FX:0] mo; // mantissa output
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reg [FX:0] mo1; // mantissa output
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reg [FX:0] mo1; // mantissa output
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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// operands sign,exponent,mantissa
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// operands sign,exponent,mantissa
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wire sa, sb;
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wire sa, sb;
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wire [EMSB:0] xa, xb;
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wire [EMSB:0] xa, xb;
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wire [FMSB:0] ma, mb;
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wire [FMSB:0] ma, mb;
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wire [FMSB+1:0] fracta, fractb;
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wire [FMSB+1:0] fracta, fractb;
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wire [FMSB+1:0] fracta1, fractb1;
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wire [FMSB+1:0] fracta1, fractb1;
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// which has greater magnitude ? Used for sign calc
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// which has greater magnitude ? Used for sign calc
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wire xa_gt_xb = xa > xb;
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wire xa_gt_xb = xa > xb;
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wire xa_gt_xb1;
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wire xa_gt_xb1;
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wire a_gt_b = xa_gt_xb || (xa==xb && ma > mb);
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wire a_gt_b = xa_gt_xb || (xa==xb && ma > mb);
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wire a_gt_b1;
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wire a_gt_b1;
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wire az, bz; // operand a,b is zero
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wire az, bz; // operand a,b is zero
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wire adn, bdn; // a,b denormalized ?
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wire adn, bdn; // a,b denormalized ?
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wire xaInf, xbInf;
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wire xaInf, xbInf;
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wire aInf, bInf, aInf1, bInf1;
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wire aInf, bInf, aInf1, bInf1;
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wire aNan, bNan, aNan1, bNan1;
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wire aNan, bNan, aNan1, bNan1;
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wire [EMSB:0] xad = xa|adn; // operand a exponent, compensated for denormalized numbers
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wire [EMSB:0] xad = xa|adn; // operand a exponent, compensated for denormalized numbers
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wire [EMSB:0] xbd = xb|bdn; // operand b exponent, compensated for denormalized numbers
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wire [EMSB:0] xbd = xb|bdn; // operand b exponent, compensated for denormalized numbers
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fpDecomp #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecomp #(WID) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecomp #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .man(mb), .fract(fractb), .xz(bdn), .vz(bz), .xinf(xbInf), .inf(bInf), .nan(bNan) );
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fpDecomp #(WID) u1b (.i(b), .sgn(sb), .exp(xb), .man(mb), .fract(fractb), .xz(bdn), .vz(bz), .xinf(xbInf), .inf(bInf), .nan(bNan) );
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// Figure out which operation is really needed an add or
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// Figure out which operation is really needed an add or
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// subtract ?
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// subtract ?
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// If the signs are the same, use the orignal op,
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// If the signs are the same, use the orignal op,
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// otherwise flip the operation
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// otherwise flip the operation
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// a + b = add,+
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// a + b = add,+
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// a + -b = sub, so of larger
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// a + -b = sub, so of larger
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// -a + b = sub, so of larger
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// -a + b = sub, so of larger
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// -a + -b = add,-
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// -a + -b = add,-
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// a - b = sub, so of larger
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// a - b = sub, so of larger
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// a - -b = add,+
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// a - -b = add,+
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// -a - b = add,-
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// -a - b = add,-
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// -a - -b = sub, so of larger
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// -a - -b = sub, so of larger
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wire realOp = op ^ sa ^ sb;
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wire realOp = op ^ sa ^ sb;
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wire realOp1;
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wire realOp1;
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wire op1;
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wire op1;
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// Find out if the result will be zero.
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// Find out if the result will be zero.
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wire resZero = (realOp && xa==xb && ma==mb) || // subtract, same magnitude
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wire resZero = (realOp && xa==xb && ma==mb) || // subtract, same magnitude
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(az & bz); // both a,b zero
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(az & bz); // both a,b zero
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// Compute output exponent
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// Compute output exponent
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//
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//
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// The output exponent is the larger of the two exponents,
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// The output exponent is the larger of the two exponents,
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// unless a subtract operation is in progress and the two
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// unless a subtract operation is in progress and the two
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// numbers are equal, in which case the exponent should be
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// numbers are equal, in which case the exponent should be
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// zero.
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// zero.
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always @(xaInf,xbInf,resZero,xa,xb,xa_gt_xb)
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always @(xaInf,xbInf,resZero,xa,xb,xa_gt_xb)
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xo1 = (xaInf&xbInf) ? xa : resZero ? 0 : xa_gt_xb ? xa : xb;
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xo1 = (xaInf&xbInf) ? xa : resZero ? 0 : xa_gt_xb ? xa : xb;
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// Compute output sign
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// Compute output sign
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reg so1;
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reg so1;
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always @*
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always @*
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case ({resZero,sa,op,sb}) // synopsys full_case parallel_case
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case ({resZero,sa,op,sb}) // synopsys full_case parallel_case
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4'b0000: so1 <= 0; // + + + = +
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4'b0000: so1 <= 0; // + + + = +
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4'b0001: so1 <= !a_gt_b; // + + - = sign of larger
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4'b0001: so1 <= !a_gt_b; // + + - = sign of larger
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4'b0010: so1 <= !a_gt_b; // + - + = sign of larger
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4'b0010: so1 <= !a_gt_b; // + - + = sign of larger
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4'b0011: so1 <= 0; // + - - = +
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4'b0011: so1 <= 0; // + - - = +
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4'b0100: so1 <= a_gt_b; // - + + = sign of larger
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4'b0100: so1 <= a_gt_b; // - + + = sign of larger
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4'b0101: so1 <= 1; // - + - = -
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4'b0101: so1 <= 1; // - + - = -
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4'b0110: so1 <= 1; // - - + = -
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4'b0110: so1 <= 1; // - - + = -
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4'b0111: so1 <= a_gt_b; // - - - = sign of larger
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4'b0111: so1 <= a_gt_b; // - - - = sign of larger
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4'b1000: so1 <= 0; // A + B, sign = +
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4'b1000: so1 <= 0; // A + B, sign = +
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4'b1001: so1 <= rm==3; // A + -B, sign = + unless rounding down
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4'b1001: so1 <= rm==3; // A + -B, sign = + unless rounding down
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4'b1010: so1 <= rm==3; // A - B, sign = + unless rounding down
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4'b1010: so1 <= rm==3; // A - B, sign = + unless rounding down
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4'b1011: so1 <= 0; // +A - -B, sign = +
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4'b1011: so1 <= 0; // +A - -B, sign = +
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4'b1100: so1 <= rm==3; // -A + B, sign = + unless rounding down
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4'b1100: so1 <= rm==3; // -A + B, sign = + unless rounding down
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4'b1101: so1 <= 1; // -A + -B, sign = -
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4'b1101: so1 <= 1; // -A + -B, sign = -
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4'b1110: so1 <= 1; // -A - +B, sign = -
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4'b1110: so1 <= 1; // -A - +B, sign = -
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4'b1111: so1 <= rm==3; // -A - -B, sign = + unless rounding down
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4'b1111: so1 <= rm==3; // -A - -B, sign = + unless rounding down
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endcase
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endcase
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delay2 #(EMSB+1) d1(.clk(clk), .ce(ce), .i(xo1), .o(xo) );
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delay2 #(EMSB+1) d1(.clk(clk), .ce(ce), .i(xo1), .o(xo) );
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delay2 #(1) d2(.clk(clk), .ce(ce), .i(so1), .o(so) );
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delay2 #(1) d2(.clk(clk), .ce(ce), .i(so1), .o(so) );
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// Compute the difference in exponents, provides shift amount
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// Compute the difference in exponents, provides shift amount
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wire [EMSB:0] xdiff = xa_gt_xb ? xad - xbd : xbd - xad;
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wire [EMSB:0] xdiff = xa_gt_xb ? xad - xbd : xbd - xad;
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wire [6:0] xdif = xdiff > FMSB+3 ? FMSB+3 : xdiff;
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wire [6:0] xdif = xdiff > FMSB+3 ? FMSB+3 : xdiff;
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wire [6:0] xdif1;
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wire [6:0] xdif1;
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// determine which fraction to denormalize
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// determine which fraction to denormalize
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wire [FMSB+1:0] mfs = xa_gt_xb ? fractb : fracta;
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wire [FMSB+1:0] mfs = xa_gt_xb ? fractb : fracta;
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wire [FMSB+1:0] mfs1;
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wire [FMSB+1:0] mfs1;
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// Determine the sticky bit
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// Determine the sticky bit
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wire sticky, sticky1;
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wire sticky, sticky1;
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generate
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generate
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begin
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begin
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if (WID==128)
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if (WID==128)
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redor128 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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redor128 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==96)
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else if (WID==96)
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redor96 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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redor96 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==80)
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else if (WID==80)
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redor80 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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redor80 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==64)
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else if (WID==64)
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redor64 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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redor64 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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else if (WID==32)
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else if (WID==32)
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redor32 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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redor32 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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end
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end
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endgenerate
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endgenerate
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// register inputs to shifter and shift
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// register inputs to shifter and shift
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delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky), .o(sticky1) );
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delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky), .o(sticky1) );
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delay1 #(7) d15(.clk(clk), .ce(ce), .i(xdif), .o(xdif1) );
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delay1 #(7) d15(.clk(clk), .ce(ce), .i(xdif), .o(xdif1) );
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delay1 #(FMSB+2) d14(.clk(clk), .ce(ce), .i(mfs), .o(mfs1) );
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delay1 #(FMSB+2) d14(.clk(clk), .ce(ce), .i(mfs), .o(mfs1) );
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wire [FMSB+3:0] md1 = ({mfs1,2'b0} >> xdif1)|sticky1;
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wire [FMSB+3:0] md1 = ({mfs1,2'b0} >> xdif1)|sticky1;
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// sync control signals
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// sync control signals
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delay1 #(1) d4 (.clk(clk), .ce(ce), .i(xa_gt_xb), .o(xa_gt_xb1) );
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delay1 #(1) d4 (.clk(clk), .ce(ce), .i(xa_gt_xb), .o(xa_gt_xb1) );
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delay1 #(1) d17(.clk(clk), .ce(ce), .i(a_gt_b), .o(a_gt_b1) );
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delay1 #(1) d17(.clk(clk), .ce(ce), .i(a_gt_b), .o(a_gt_b1) );
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delay1 #(1) d5 (.clk(clk), .ce(ce), .i(realOp), .o(realOp1) );
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delay1 #(1) d5 (.clk(clk), .ce(ce), .i(realOp), .o(realOp1) );
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delay1 #(FMSB+2) d5a(.clk(clk), .ce(ce), .i(fracta), .o(fracta1) );
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delay1 #(FMSB+2) d5a(.clk(clk), .ce(ce), .i(fracta), .o(fracta1) );
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delay1 #(FMSB+2) d6a(.clk(clk), .ce(ce), .i(fractb), .o(fractb1) );
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delay1 #(FMSB+2) d6a(.clk(clk), .ce(ce), .i(fractb), .o(fractb1) );
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delay1 #(1) d7 (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay1 #(1) d7 (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay1 #(1) d8 (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay1 #(1) d8 (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay1 #(1) d9 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay1 #(1) d9 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay1 #(1) d10(.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay1 #(1) d10(.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay1 #(1) d11(.clk(clk), .ce(ce), .i(op), .o(op1) );
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delay1 #(1) d11(.clk(clk), .ce(ce), .i(op), .o(op1) );
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// Sort operands and perform add/subtract
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// Sort operands and perform add/subtract
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// addition can generate an extra bit, subtract can't go negative
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// addition can generate an extra bit, subtract can't go negative
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wire [FMSB+3:0] oa = xa_gt_xb1 ? {fracta1,2'b0} : md1;
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wire [FMSB+3:0] oa = xa_gt_xb1 ? {fracta1,2'b0} : md1;
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wire [FMSB+3:0] ob = xa_gt_xb1 ? md1 : {fractb1,2'b0};
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wire [FMSB+3:0] ob = xa_gt_xb1 ? md1 : {fractb1,2'b0};
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wire [FMSB+3:0] oaa = a_gt_b1 ? oa : ob;
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wire [FMSB+3:0] oaa = a_gt_b1 ? oa : ob;
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wire [FMSB+3:0] obb = a_gt_b1 ? ob : oa;
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wire [FMSB+3:0] obb = a_gt_b1 ? ob : oa;
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wire [FMSB+4:0] mab = realOp1 ? oaa - obb : oaa + obb;
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wire [FMSB+4:0] mab = realOp1 ? oaa - obb : oaa + obb;
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wire xoinf = &xo;
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always @*
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always @*
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casez({aInf1&bInf1,aNan1,bNan1})
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casez({aInf1&bInf1,aNan1,bNan1,xoinf})
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3'b1??: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b1???: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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3'b01?: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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4'b01??: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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3'b001: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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4'b001?: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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4'b0001: mo1 = 1'd0;
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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endcase
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endcase
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delay1 #(FX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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delay1 #(FX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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endmodule
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endmodule
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module fpAddsubnr(clk, ce, rm, op, a, b, o);
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module fpAddsubnr(clk, ce, rm, op, a, b, o);
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parameter WID = 128;
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parameter WID = 128;
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localparam MSB = WID-1;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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WID==24 ? 15 : 9;
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam FX = (FMSB+2)*2-1; // the MSB of the expanded fraction
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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localparam EX = FX + 1 + EMSB + 1 + 1 - 1;
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input clk; // system clock
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input clk; // system clock
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input ce; // core clock enable
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input ce; // core clock enable
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input op; // operation 0 = add, 1 = subtract
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input op; // operation 0 = add, 1 = subtract
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input [MSB:0] a; // operand a
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input [MSB:0] a; // operand a
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input [MSB:0] b; // operand b
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input [MSB:0] b; // operand b
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output [MSB:0] o; // output
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output [MSB:0] o; // output
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wire [EX:0] o1;
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wire [EX:0] o1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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fpAddsub #(WID) u1 (clk, ce, rm, op, a, b, o1);
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fpAddsub #(WID) u1 (clk, ce, rm, op, a, b, o1);
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
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fpNormalize #(WID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRoundReg #(WID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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endmodule
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endmodule
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