// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// DFPCompare96.sv
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// DFPCompare96.sv
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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import DFPPkg::*;
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import DFPPkg::*;
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module DFPCompare96(a, b, o);
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module DFPCompare96(a, b, o);
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input DFP96 a;
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input DFP96 a;
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input DFP96 b;
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input DFP96 b;
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output reg [11:0] o ='d0;
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output reg [11:0] o ='d0;
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localparam N=34; // number of BCD digits
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localparam N=25; // number of BCD digits
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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DFP96U au;
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DFP96U au;
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DFP96U bu;
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DFP96U bu;
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DFPUnpack96 u00 (a, au);
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DFPUnpack96 u00 (a, au);
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DFPUnpack96 u01 (b, bu);
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DFPUnpack96 u01 (b, bu);
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reg sa, sb;
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reg sa, sb;
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always_comb
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always_comb
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sa = au.sign;
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sa = au.sign;
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always_comb
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always_comb
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sb = bu.sign;
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sb = bu.sign;
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wire az = ~|{au.exp,au.sig};
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wire az = ~|{au.exp,au.sig};
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wire bz = ~|{bu.exp,bu.sig};
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wire bz = ~|{bu.exp,bu.sig};
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wire unordered = au.nan | bu.nan;
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wire unordered = au.nan | bu.nan;
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wire eq = !unordered & ((az & bz) || (a==b)); // special test for zero
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wire eq = !unordered & ((az & bz) || (a==b)); // special test for zero
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wire gt1 = {au.exp,au.sig} > {bu.exp,bu.sig};
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wire gt1 = {au.exp,au.sig} > {bu.exp,bu.sig};
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wire lt1 = {au.exp,au.sig} < {bu.exp,bu.sig};
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wire lt1 = {au.exp,au.sig} < {bu.exp,bu.sig};
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wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1;
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wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1;
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always_comb
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always_comb
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begin
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begin
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o[0] = eq;
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o[0] = eq;
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o[1] = lt;
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o[1] = lt;
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o[2] = lt|eq;
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o[2] = lt|eq;
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o[3] = lt1;
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o[3] = lt1;
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o[4] = unordered;
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o[4] = unordered;
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o[5] = ~eq;
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o[5] = ~eq;
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o[6] = ~lt;
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o[6] = ~lt;
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o[7] = ~(lt|eq);
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o[7] = ~(lt|eq);
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o[8] = ~lt1;
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o[8] = ~lt1;
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o[9] = ~unordered;
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o[9] = ~unordered;
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o[10] = 1'b0;
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o[10] = 1'b0;
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o[11] = lt;
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o[11] = lt;
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end
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end
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// an unorder comparison will signal a nan exception
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// an unorder comparison will signal a nan exception
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//assign nanx = op!=`FCOR && op!=`FCUN && unordered;
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//assign nanx = op!=`FCOR && op!=`FCUN && unordered;
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endmodule
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endmodule
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