// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// DFPDecompose.sv
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// DFPDecompose.sv
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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module DFPDecompose(i, sgn, sx, exp, sig, xz, vz, inf, nan);
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module DFPDecompose(i, sgn, sx, exp, sig, xz, vz, inf, nan);
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input [127:0] i;
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input [127:0] i;
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output sgn;
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output sgn;
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output sx;
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output sx;
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output [15:0] exp;
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output [15:0] exp;
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output [95:0] sig;
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output [107:0] sig;
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output xz;
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output xz;
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output vz;
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output vz;
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output inf;
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output inf;
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output nan;
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output nan;
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assign nan = i[127];
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assign nan = i[127];
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assign sgn = i[126];
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assign sgn = i[126];
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assign inf = i[125];
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assign inf = i[125];
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assign sx = i[124];
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assign sx = i[124];
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assign exp = i[123:108];
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assign exp = i[123:108];
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assign sig = i[107:0];
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assign sig = i[107:0];
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assign xz = ~|exp;
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assign xz = ~|exp;
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assign vz = ~|{exp,sig};
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assign vz = ~|{exp,sig};
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endmodule
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endmodule
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module DFPDecomposeReg(clk, ce, i, sgn, sx, exp, sig, xz, vz, inf, nan);
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module DFPDecomposeReg(clk, ce, i, sgn, sx, exp, sig, xz, vz, inf, nan);
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input clk;
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input clk;
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input ce;
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input ce;
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input [127:0] i;
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input [127:0] i;
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output reg sgn;
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output reg sgn;
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output reg sx;
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output reg sx;
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output reg [15:0] exp;
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output reg [15:0] exp;
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output reg [107:0] sig;
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output reg [107:0] sig;
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output reg xz;
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output reg xz;
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output reg vz;
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output reg vz;
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output reg inf;
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output reg inf;
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output reg nan;
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output reg nan;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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nan <= i[127];
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nan <= i[127];
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sgn <= i[126];
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sgn <= i[126];
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inf <= i[125];
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inf <= i[125];
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sx <= i[124];
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sx <= i[124];
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exp <= i[123:108];
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exp <= i[123:108];
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sig <= i[107:0];
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sig <= i[107:0];
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xz <= ~|exp;
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xz <= ~|exp;
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vz <= ~|{exp,sig};
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vz <= ~|{exp,sig};
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end
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end
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endmodule
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endmodule
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