// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// DFPSqrt96.sv
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// DFPSqrt96.sv
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// - decimal floating point square root
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// - decimal floating point square root
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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import DFPPkg::*;
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import DFPPkg::*;
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import fp::*;
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module DFPSqrt96(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
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module DFPSqrt96(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
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parameter N=25;
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parameter N=25;
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localparam pShiftAmt =
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FPWID==80 ? 48 :
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FPWID==64 ? 36 :
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FPWID==32 ? 7 : (FMSB+1-16);
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input DFP96 a;
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input DFP96 a;
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output DFP96UD o;
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output DFP96UD o;
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output done;
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output done;
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output sqrinf;
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output sqrinf;
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output sqrneg;
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output sqrneg;
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// registered outputs
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// registered outputs
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reg sign_exe;
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reg sign_exe;
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reg inf;
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reg inf;
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reg overflow;
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reg overflow;
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reg underflow;
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reg underflow;
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wire sign = 1'b0;
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wire so;
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wire so;
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wire [13:0] xo;
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wire [13:0] xo;
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wire [(N+1)*4*2-1:0] mo;
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wire [(N+1)*4*2-1:0] mo;
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// constants
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// constants
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wire [13:0] infXp = 12'hBFF; // infinite / NaN - all ones
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wire [13:0] infXp = 12'hBFF; // infinite / NaN - all ones
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// The following is a template for a quiet nan. (MSB=1)
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// The following is a template for a quiet nan. (MSB=1)
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wire [N*4-1:0] qNaN = {4'h1,{N*4-4{1'b0}}};
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wire [N*4-1:0] qNaN = {4'h1,{N*4-4{1'b0}}};
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// variables
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// variables
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wire [13:0] ex1; // sum of exponents
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wire [13:0] ex1; // sum of exponents
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wire ex1c;
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wire ex1c;
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wire [(N+1)*4*2-1:0] sqrto;
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wire [(N+1)*4*2-1:0] sqrto;
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// Operands
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// Operands
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reg sa; // sign bit
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reg sa; // sign bit
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reg [11:0] xa; // exponent bits
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reg [11:0] xa; // exponent bits
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reg [N*4-1:0] siga;
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reg [N*4-1:0] siga;
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reg a_dn; // a/b is denormalized
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reg a_dn; // a/b is denormalized
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reg az;
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reg az;
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reg aInf;
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reg aInf;
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reg aNan;
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reg aNan;
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wire done1;
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wire done1;
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wire [7:0] lzcnt;
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wire [7:0] lzcnt;
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wire [N*4-1:0] aa;
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wire [N*4-1:0] aa;
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DFP96U au;
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DFP96U au;
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// - decode the input operand
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// - decode the input operand
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// - derive basic information
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// - derive basic information
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// - calculate exponent
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// - calculate exponent
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// - calculate fraction
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// - calculate fraction
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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DFPUnpack96 u01 (a, au);
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DFPUnpack96 u01 (a, au);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sa <= au.sign;
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if (ce) sa <= au.sign;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xa <= au.exp;
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if (ce) xa <= au.exp;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) siga <= au.sig;
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if (ce) siga <= au.sig;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) a_dn <= au.exp==12'd0;
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if (ce) a_dn <= au.exp==12'd0;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) az <= au.exp==12'd0 && au.sig==100'd0;
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if (ce) az <= au.exp==12'd0 && au.sig==100'd0;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) aInf <= au.infinity;
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if (ce) aInf <= au.infinity;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) aNan <= au.nan;
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if (ce) aNan <= au.nan;
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assign ex1 = xa + 1'd1;
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assign ex1 = xa + 1'd1;
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assign xo = ex1 >> 1'd1;
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assign xo = ex1 >> 1'd1;
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assign so = 1'b0; // square root of positive numbers only
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assign so = 1'b0; // square root of positive numbers only
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assign mo = aNan ? {4'h1,aa[N*4-1:0],{N*4{1'b0}}} : sqrto; //(sqrto << pShiftAmt);
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assign mo = aNan ? {4'h1,aa[N*4-1:0],{N*4{1'b0}}} : sqrto; //(sqrto << pShiftAmt);
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assign sqrinf = aInf;
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assign sqrinf = aInf;
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assign sqrneg = !az & so;
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assign sqrneg = !az & so;
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wire [(N+1)*4-1:0] siga1 = xa[0] ? {siga,4'h0} : {4'h0,siga};
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wire [(N+1)*4-1:0] siga1 = xa[0] ? {siga,4'h0} : {4'h0,siga};
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wire ldd;
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wire ldd;
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(ld), .o(ldd));
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(ld), .o(ldd));
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// Ensure an even number of digits are processed.
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// Ensure an even number of digits are processed.
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dfisqrt #((N+2)&-2) u2
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dfisqrt #((N+2)&-2) u2
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ce(ce),
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.ce(ce),
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.ld(ldd),
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.ld(ldd),
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.a({4'h0,siga1}),
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.a({4'h0,siga1}),
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.o(sqrto),
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.o(sqrto),
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.done(done)
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.done(done)
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);
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);
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always @*
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always @*
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casez({aNan,sqrinf,sqrneg})
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casez({aNan,sqrinf,sqrneg})
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3'b1??:
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3'b1??:
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begin
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begin
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o.sign <= sign;
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o.sign <= sign;
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o.nan <= 1'b1;
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o.nan <= 1'b1;
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o.exp <= 12'hBFF;
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o.exp <= 12'hBFF;
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o.sig <= {siga,{N*4-4{1'b0}}};
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o.sig <= {siga,{N*4-4{1'b0}}};
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end
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end
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3'b01?:
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3'b01?:
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begin
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begin
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o.sign <= sign;
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o.sign <= sign;
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o.nan <= 1'b1;
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o.nan <= 1'b1;
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o.exp <= 12'hBFF;
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o.exp <= 12'hBFF;
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o.sig <= {4'h1,qNaN|4'h5,{N*4-4{1'b0}}};
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o.sig <= {4'h1,qNaN|4'h5,{N*4-4{1'b0}}};
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end
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end
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3'b001:
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3'b001:
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begin
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begin
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o.sign <= sign;
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o.sign <= sign;
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o.nan <= 1'b1;
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o.nan <= 1'b1;
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o.exp <= 12'hBFF;
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o.exp <= 12'hBFF;
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o.sig <= {4'h1,qNaN|4'h6,{N*4-4{1'b0}}};
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o.sig <= {4'h1,qNaN|4'h6,{N*4-4{1'b0}}};
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end
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end
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default:
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default:
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begin
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begin
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o.sign <= 1'b0;
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o.sign <= 1'b0;
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o.nan <= 1'b0;
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o.nan <= 1'b0;
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o.exp <= xo;
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o.exp <= xo;
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o.sig <= mo;
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o.sig <= mo;
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end
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end
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endcase
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endcase
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endmodule
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endmodule
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module DFPSqrt96nr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
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module DFPSqrt96nr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
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parameter N=25;
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parameter N=25;
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input DFP96 a;
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input DFP96 a;
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output DFP96 o;
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output DFP96 o;
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input [2:0] rm;
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input [2:0] rm;
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output done;
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output done;
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output inf;
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output inf;
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output sqrinf;
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output sqrinf;
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output sqrneg;
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output sqrneg;
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wire DFP96UD o1;
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wire DFP96UD o1;
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wire inf1;
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wire inf1;
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wire DFP96UN fpn0;
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wire DFP96UN fpn0;
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wire done1;
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wire done1;
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wire done2;
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wire done2;
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DFPSqrt96 #(.N(N)) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
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DFPSqrt96 #(.N(N)) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
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DFPNormalize96 #(.N(N)) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPNormalize96 #(.N(N)) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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DFPRound96 #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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DFPRound96 #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done2));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done2));
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assign done = done1&done2;
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assign done = done1&done2;
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endmodule
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endmodule
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