// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpAddsub.v
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// fpAddsub.v
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// - floating point adder/subtracter
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// - floating point adder/subtracter
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// - ten cycle latency
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// - ten cycle latency
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// - can issue every clock cycle
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// - can issue every clock cycle
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// - parameterized FPWIDth
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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`include "fpConfig.sv"
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`include "fpConfig.sv"
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module fpAddsub(clk, ce, rm, op, a, b, o);
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module fpAddsub(clk, ce, rm, op, a, b, o);
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parameter FPWID = 128;
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parameter FPWID = 128;
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`include "fpSize.sv"
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`include "fpSize.sv"
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input clk; // system clock
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input clk; // system clock
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input ce; // core clock enable
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input ce; // core clock enable
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input op; // operation 0 = add, 1 = subtract
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input op; // operation 0 = add, 1 = subtract
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input [MSB:0] a; // operand a
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input [MSB:0] a; // operand a
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input [MSB:0] b; // operand b
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input [MSB:0] b; // operand b
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output [EX:0] o; // output
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output [EX:0] o; // output
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wire so; // sign output
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wire so; // sign output
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wire [EMSB:0] xo; // de normalized exponent output
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wire [EMSB:0] xo; // de normalized exponent output
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reg [FX:0] mo; // mantissa output
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reg [FX:0] mo; // mantissa output
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock edge #1
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// Clock edge #1
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// - Decompose inputs into more digestible values.
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// - Decompose inputs into more digestible values.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire [MSB:0] a1;
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wire [MSB:0] a1;
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wire [MSB:0] b1;
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wire [MSB:0] b1;
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wire sa1, sb1;
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wire sa1, sb1;
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wire [EMSB:0] xa1, xb1;
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wire [EMSB:0] xa1, xb1;
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wire [FMSB:0] ma1, mb1;
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wire [FMSB:0] ma1, mb1;
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wire [FMSB+1:0] fracta1, fractb1;
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wire [FMSB+1:0] fracta1, fractb1;
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wire adn1, bdn1; // a,b denormalized ?
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wire adn1, bdn1; // a,b denormalized ?
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wire xaInf1, xbInf1;
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wire xaInf1, xbInf1;
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wire aInf1, bInf1;
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wire aInf1, bInf1;
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wire aNan1, bNan1;
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wire aNan1, bNan1;
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wire az1, bz1; // operand a,b is zero
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wire az1, bz1; // operand a,b is zero
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wire op1;
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wire op1;
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fpDecompReg #(FPWID) u1a (.clk(clk), .ce(ce), .i(a), .o(a1), .sgn(sa1), .exp(xa1), .man(ma1), .fract(fracta1), .xz(adn1), .vz(az1), .xinf(xaInf1), .inf(aInf1), .nan(aNan1) );
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fpDecompReg #(FPWID) u1a (.clk(clk), .ce(ce), .i(a), .o(a1), .sgn(sa1), .exp(xa1), .man(ma1), .fract(fracta1), .xz(adn1), .vz(az1), .xinf(xaInf1), .inf(aInf1), .nan(aNan1) );
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fpDecompReg #(FPWID) u1b (.clk(clk), .ce(ce), .i(b), .o(b1), .sgn(sb1), .exp(xb1), .man(mb1), .fract(fractb1), .xz(bdn1), .vz(bz1), .xinf(xbInf1), .inf(bInf1), .nan(bNan1) );
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fpDecompReg #(FPWID) u1b (.clk(clk), .ce(ce), .i(b), .o(b1), .sgn(sb1), .exp(xb1), .man(mb1), .fract(fractb1), .xz(bdn1), .vz(bz1), .xinf(xbInf1), .inf(bInf1), .nan(bNan1) );
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delay1 #(1) dop1(.clk(clk), .ce(ce), .i(op), .o(op1) );
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delay1 #(1) dop1(.clk(clk), .ce(ce), .i(op), .o(op1) );
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock edge #2
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// Clock edge #2
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg xabeq2;
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reg xabeq2;
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reg mabeq2;
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reg mabeq2;
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reg anbz2;
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reg anbz2;
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reg xabInf2;
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reg xabInf2;
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reg anbInf2;
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reg anbInf2;
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wire [EMSB:0] xa2, xb2;
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wire [EMSB:0] xa2, xb2;
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wire [FMSB:0] ma2, mb2;
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wire [FMSB:0] ma2, mb2;
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// operands sign,exponent,mantissa
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// operands sign,exponent,mantissa
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wire [FMSB+1:0] fracta2, fractb2;
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wire [FMSB+1:0] fracta2, fractb2;
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wire az2, bz2; // operand a,b is zero
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wire az2, bz2; // operand a,b is zero
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reg xa_gt_xb2;
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reg xa_gt_xb2;
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reg var2;
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reg var2;
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reg [EMSB:0] xad2;
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reg [EMSB:0] xad2;
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reg [EMSB:0] xbd2;
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reg [EMSB:0] xbd2;
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reg realOp2;
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reg realOp2;
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delay1 #(EMSB+1) dxa2(.clk(clk), .ce(ce), .i(xa1), .o(xa2) );
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delay1 #(EMSB+1) dxa2(.clk(clk), .ce(ce), .i(xa1), .o(xa2) );
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delay1 #(EMSB+1) dxb2(.clk(clk), .ce(ce), .i(xb1), .o(xb2) );
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delay1 #(EMSB+1) dxb2(.clk(clk), .ce(ce), .i(xb1), .o(xb2) );
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delay1 #(FMSB+1) dma2(.clk(clk), .ce(ce), .i(ma1), .o(ma2) );
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delay1 #(FMSB+1) dma2(.clk(clk), .ce(ce), .i(ma1), .o(ma2) );
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delay1 #(FMSB+1) dmb2(.clk(clk), .ce(ce), .i(mb1), .o(mb2) );
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delay1 #(FMSB+1) dmb2(.clk(clk), .ce(ce), .i(mb1), .o(mb2) );
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delay1 #(1) daz2(.clk(clk), .ce(ce), .i(az1), .o(az2) );
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delay1 #(1) daz2(.clk(clk), .ce(ce), .i(az1), .o(az2) );
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delay1 #(1) dbz2(.clk(clk), .ce(ce), .i(bz1), .o(bz2) );
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delay1 #(1) dbz2(.clk(clk), .ce(ce), .i(bz1), .o(bz2) );
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delay1 #(FMSB+2) dfracta2(.clk(clk), .ce(ce), .i(fracta1), .o(fracta2) );
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delay1 #(FMSB+2) dfracta2(.clk(clk), .ce(ce), .i(fracta1), .o(fracta2) );
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delay1 #(FMSB+2) dfractb2(.clk(clk), .ce(ce), .i(fractb1), .o(fractb2) );
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delay1 #(FMSB+2) dfractb2(.clk(clk), .ce(ce), .i(fractb1), .o(fractb2) );
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xa_gt_xb2 <= xa1 > xb1;
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if (ce) xa_gt_xb2 <= xa1 > xb1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) var2 <= (xa1==xb1 && ma1 > mb1);
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if (ce) var2 <= (xa1==xb1 && ma1 > mb1);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xad2 <= xa1|adn1; // operand a exponent, compensated for denormalized numbers
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if (ce) xad2 <= xa1|adn1; // operand a exponent, compensated for denormalized numbers
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xbd2 <= xb1|bdn1; // operand b exponent, compensated for denormalized numbers
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if (ce) xbd2 <= xb1|bdn1; // operand b exponent, compensated for denormalized numbers
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xabeq2 <= xa1==xb1;
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if (ce) xabeq2 <= xa1==xb1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mabeq2 <= ma1==mb1;
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if (ce) mabeq2 <= ma1==mb1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) anbz2 <= az1 & bz1;
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if (ce) anbz2 <= az1 & bz1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xabInf2 <= xaInf1 & xbInf1;
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if (ce) xabInf2 <= xaInf1 & xbInf1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) anbInf2 <= aInf1 & bInf1;
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if (ce) anbInf2 <= aInf1 & bInf1;
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// Figure out which operation is really needed an add or
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// Figure out which operation is really needed an add or
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// subtract ?
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// subtract ?
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// If the signs are the same, use the orignal op,
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// If the signs are the same, use the orignal op,
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// otherwise flip the operation
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// otherwise flip the operation
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// a + b = add,+
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// a + b = add,+
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// a + -b = sub, so of larger
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// a + -b = sub, so of larger
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// -a + b = sub, so of larger
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// -a + b = sub, so of larger
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// -a + -b = add,-
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// -a + -b = add,-
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// a - b = sub, so of larger
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// a - b = sub, so of larger
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// a - -b = add,+
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// a - -b = add,+
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// -a - b = add,-
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// -a - b = add,-
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// -a - -b = sub, so of larger
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// -a - -b = sub, so of larger
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always @(posedge clk)
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always @(posedge clk)
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if (ce) realOp2 <= op1 ^ sa1 ^ sb1;
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if (ce) realOp2 <= op1 ^ sa1 ^ sb1;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock edge #3
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// Clock edge #3
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire [EMSB:0] xa3, xb3;
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wire [EMSB:0] xa3, xb3;
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wire xa_gt_xb3;
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wire xa_gt_xb3;
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reg x_gt_b3;
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reg x_gt_b3;
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wire xabInf3;
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wire xabInf3;
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wire sa3,sb3;
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wire sa3,sb3;
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wire op3;
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wire op3;
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wire [2:0] rm3;
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wire [2:0] rm3;
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reg [EMSB:0] xdiff3;
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reg [EMSB:0] xdiff3;
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// which has greater magnitude ? Used for sign calc
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// which has greater magnitude ? Used for sign calc
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reg a_gt_b3;
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reg a_gt_b3;
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reg resZero3;
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reg resZero3;
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reg [FMSB+1:0] mfs3;
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reg [FMSB+1:0] mfs3;
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wire aNan3, bNan3;
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delay1 #(EMSB+1) dxa3(.clk(clk), .ce(ce), .i(xa2), .o(xa3));
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delay1 #(EMSB+1) dxa3(.clk(clk), .ce(ce), .i(xa2), .o(xa3));
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delay1 #(EMSB+1) dxb3(.clk(clk), .ce(ce), .i(xb2), .o(xb3));
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delay1 #(EMSB+1) dxb3(.clk(clk), .ce(ce), .i(xb2), .o(xb3));
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delay1 #(1) dxabInf2(.clk(clk), .ce(ce), .i(xabInf2), .o(xabInf3));
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delay1 #(1) dxabInf2(.clk(clk), .ce(ce), .i(xabInf2), .o(xabInf3));
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delay1 #(1) dxagtxb2(.clk(clk), .ce(ce), .i(xa_gt_xb2), .o(xa_gt_xb3));
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delay1 #(1) dxagtxb2(.clk(clk), .ce(ce), .i(xa_gt_xb2), .o(xa_gt_xb3));
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delay2 #(1) dsa2(.clk(clk), .ce(ce), .i(sa1), .o(sa3));
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delay2 #(1) dsa2(.clk(clk), .ce(ce), .i(sa1), .o(sa3));
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delay2 #(1) dsb2(.clk(clk), .ce(ce), .i(sb1), .o(sb3));
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delay2 #(1) dsb2(.clk(clk), .ce(ce), .i(sb1), .o(sb3));
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delay2 #(1) dop2(.clk(clk), .ce(ce), .i(op1), .o(op3));
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delay2 #(1) dop2(.clk(clk), .ce(ce), .i(op1), .o(op3));
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delay3 #(3) drm2(.clk(clk), .ce(ce), .i(rm), .o(rm3));
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delay3 #(3) drm2(.clk(clk), .ce(ce), .i(rm), .o(rm3));
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delay2 #(1) dan2(.clk(clk), .ce(ce), .i(aNan1), .o(aNan3));
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delay2 #(1) dbn2(.clk(clk), .ce(ce), .i(bNan1), .o(bNan3));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) a_gt_b3 <= xa_gt_xb2 || var2;
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if (ce) a_gt_b3 <= xa_gt_xb2 || var2;
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// Find out if the result will be zero.
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// Find out if the result will be zero.
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always @(posedge clk)
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always @(posedge clk)
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if (ce) resZero3 <= (realOp2 & xabeq2 & mabeq2) | anbz2; // subtract, same magnitude, both a,b zero
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if (ce) resZero3 <= (realOp2 & xabeq2 & mabeq2) | anbz2; // subtract, same magnitude, both a,b zero
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// Compute the difference in exponents, provides shift amount
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// Compute the difference in exponents, provides shift amount
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xdiff3 <= xa_gt_xb2 ? xad2 - xbd2 : xbd2 - xad2;
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if (ce) xdiff3 <= xa_gt_xb2 ? xad2 - xbd2 : xbd2 - xad2;
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// determine which fraction to denormalize
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// determine which fraction to denormalize
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mfs3 <= xa_gt_xb2 ? fractb2 : fracta2;
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if (ce) mfs3 <= xa_gt_xb2 ? fractb2 : fracta2;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock edge #4
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// Clock edge #4
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// Compute output exponent
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// Compute output exponent
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//
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//
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// The output exponent is the larger of the two exponents, unless a subtract
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// The output exponent is the larger of the two exponents, unless a subtract
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// operation is in progress and the two numbers are equal, in which case the
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// operation is in progress and the two numbers are equal, in which case the
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// exponent should be zero.
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// exponent should be zero.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [EMSB:0] xdif4;
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reg [EMSB:0] xdif4;
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wire [FMSB+1:0] mfs4;
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wire [FMSB+1:0] mfs4;
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reg [EMSB:0] xo4; // de normalized exponent output
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reg [EMSB:0] xo4; // de normalized exponent output
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reg so4;
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reg so4;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xo4 <= xabInf3 ? xa3 : resZero3 ? {EMSB+1{1'b0}} : xa_gt_xb3 ? xa3 : xb3;
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if (ce) xo4 <= xabInf3 ? xa3 : resZero3 ? {EMSB+1{1'b0}} : xa_gt_xb3 ? xa3 : xb3;
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// Compute output sign
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// Compute output sign
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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casez ({aNan3,bNan3,resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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4'b0000: so4 <= 0; // + + + = +
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6'b10????: so4 <= sa3;
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4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
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6'b01????: so4 <= sb3;
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4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
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6'b11????: so4 <= a_gt_b3 ? sa3 : sb3;
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4'b0011: so4 <= 0; // + - - = +
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6'b000000: so4 <= 0; // + + + = +
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4'b0100: so4 <= a_gt_b3; // - + + = sign of larger
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6'b000001: so4 <= a_gt_b3 ? 1'b0 : 1'b1; // + + - = sign of larger
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4'b0101: so4 <= 1; // - + - = -
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6'b000010: so4 <= a_gt_b3 ? 1'b0 : 1'b1; // + - + = sign of larger
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4'b0110: so4 <= 1; // - - + = -
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6'b000011: so4 <= 0; // + - - = +
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4'b0111: so4 <= a_gt_b3; // - - - = sign of larger
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6'b000100: so4 <= a_gt_b3 ? 1'b1 : 1'b0; // - + + = sign of larger
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4'b1000: so4 <= 0; // A + B, sign = +
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6'b000101: so4 <= 1; // - + - = -
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4'b1001: so4 <= rm3==3'd3; // A + -B, sign = + unless rounding down
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6'b000110: so4 <= 1; // - - + = -
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4'b1010: so4 <= rm3==3'd3; // A - B, sign = + unless rounding down
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6'b000111: so4 <= a_gt_b3 ? 1'b1 : 1'b0; // - - - = sign of larger
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4'b1011: so4 <= 0; // +A - -B, sign = +
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4'b1100: so4 <= rm3==3'd3; // -A + B, sign = + unless rounding down
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6'b001000: so4 <= 0; // A + B, sign = +
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4'b1101: so4 <= 1; // -A + -B, sign = -
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6'b001001: so4 <= rm3==3'd3; // A + -B, sign = + unless rounding down
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4'b1110: so4 <= 1; // -A - +B, sign = -
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6'b001010: so4 <= rm3==3'd3; // A - B, sign = + unless rounding down
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4'b1111: so4 <= rm3==3'd3; // -A - -B, sign = + unless rounding down
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6'b001011: so4 <= 0; // +A - -B, sign = +
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6'b001100: so4 <= rm3==3'd3; // -A + B, sign = + unless rounding down
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6'b001101: so4 <= 1; // -A + -B, sign = -
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6'b001110: so4 <= 1; // -A - +B, sign = -
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6'b001111: so4 <= rm3==3'd3; // -A - -B, sign = + unless rounding down
|
endcase
|
endcase
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) xdif4 <= xdiff3 > FMSB+3 ? FMSB+3 : xdiff3;
|
if (ce) xdif4 <= xdiff3 > FMSB+3 ? FMSB+3 : xdiff3;
|
delay1 #(FMSB+2) dmsf3(.clk(clk), .ce(ce), .i(mfs3), .o(mfs4));
|
delay1 #(FMSB+2) dmsf3(.clk(clk), .ce(ce), .i(mfs3), .o(mfs4));
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock edge #5
|
// Clock edge #5
|
// Determine the sticky bit
|
// Determine the sticky bit
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
wire [EMSB:0] xdif5;
|
wire [EMSB:0] xdif5;
|
wire [FMSB+1:0] mfs5;
|
wire [FMSB+1:0] mfs5;
|
wire sticky, sticky5;
|
wire sticky, sticky5;
|
|
|
// register inputs to shifter and shift
|
// register inputs to shifter and shift
|
delay1 #(1) dstky4(.clk(clk), .ce(ce), .i(sticky), .o(sticky5) );
|
delay1 #(1) dstky4(.clk(clk), .ce(ce), .i(sticky), .o(sticky5) );
|
delay1 #(EMSB+1) dxdif4(.clk(clk), .ce(ce), .i(xdif4), .o(xdif5) );
|
delay1 #(EMSB+1) dxdif4(.clk(clk), .ce(ce), .i(xdif4), .o(xdif5) );
|
delay1 #(FMSB+2) dmsf4(.clk(clk), .ce(ce), .i(mfs4), .o(mfs5));
|
delay1 #(FMSB+2) dmsf4(.clk(clk), .ce(ce), .i(mfs4), .o(mfs5));
|
|
|
generate
|
generate
|
begin
|
begin
|
if (FPWID+`EXTRA_BITS==128)
|
if (FPWID==128)
|
redor128 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor128 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==96)
|
else if (FPWID==96)
|
redor96 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor96 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==84)
|
else if (FPWID==84)
|
redor84 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor84 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==80)
|
else if (FPWID==80)
|
redor80 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor80 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==64)
|
else if (FPWID==64)
|
redor64 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor64 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==40)
|
else if (FPWID==40)
|
redor40 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor40 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==32)
|
else if (FPWID==32)
|
redor32 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
redor32 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock edge #6
|
// Clock edge #6
|
// Shift (denormalize)
|
// Shift (denormalize)
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [FMSB+3:0] md6;
|
reg [FMSB+3:0] md6;
|
wire xa_gt_xb6;
|
wire xa_gt_xb6;
|
wire [FMSB+1:0] fracta6, fractb6;
|
wire [FMSB+1:0] fracta6, fractb6;
|
|
|
delay3 #(1) dxagtxb5(.clk(clk), .ce(ce), .i(xa_gt_xb3), .o(xa_gt_xb6));
|
delay3 #(1) dxagtxb5(.clk(clk), .ce(ce), .i(xa_gt_xb3), .o(xa_gt_xb6));
|
delay4 #(FMSB+2) dfracta5(.clk(clk), .ce(ce), .i(fracta2), .o(fracta6) );
|
delay4 #(FMSB+2) dfracta5(.clk(clk), .ce(ce), .i(fracta2), .o(fracta6) );
|
delay4 #(FMSB+2) dfractb5(.clk(clk), .ce(ce), .i(fractb2), .o(fractb6) );
|
delay4 #(FMSB+2) dfractb5(.clk(clk), .ce(ce), .i(fractb2), .o(fractb6) );
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) md6 <= ({mfs5,2'b0} >> xdif5)|sticky5;
|
if (ce) md6 <= ({mfs5,2'b0} >> xdif5)|sticky5;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock edge #7
|
// Clock edge #7
|
// Sort operands
|
// Sort operands
|
// addition can generate an extra bit, subtract can't go negative
|
// addition can generate an extra bit, subtract can't go negative
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [FMSB+3:0] oa7;
|
reg [FMSB+3:0] oa7;
|
reg [FMSB+3:0] ob7;
|
reg [FMSB+3:0] ob7;
|
wire a_gt_b7;
|
wire a_gt_b7;
|
|
|
delay4 #(1) dagtb5(.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b7));
|
delay4 #(1) dagtb5(.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b7));
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) oa7 <= xa_gt_xb6 ? {fracta6,2'b0} : md6;
|
if (ce) oa7 <= xa_gt_xb6 ? {fracta6,2'b0} : md6;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) ob7 <= xa_gt_xb6 ? md6 : {fractb6,2'b0};
|
if (ce) ob7 <= xa_gt_xb6 ? md6 : {fractb6,2'b0};
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock edge #8
|
// Clock edge #8
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [FMSB+3:0] oaa8;
|
reg [FMSB+3:0] oaa8;
|
reg [FMSB+3:0] obb8;
|
reg [FMSB+3:0] obb8;
|
wire [EMSB:0] xo8;
|
wire [EMSB:0] xo8;
|
wire realOp8;
|
wire realOp8;
|
vtdl #(.WID(1)) drealop7 (.clk(clk), .ce(ce), .a(4'd5), .d(realOp2), .q(realOp8));
|
vtdl #(.WID(1)) drealop7 (.clk(clk), .ce(ce), .a(4'd5), .d(realOp2), .q(realOp8));
|
vtdl #(.WID(EMSB+1)) dxo7(.clk(clk), .ce(ce), .a(4'd3), .d(xo4), .q(xo8));
|
vtdl #(.WID(EMSB+1)) dxo7(.clk(clk), .ce(ce), .a(4'd3), .d(xo4), .q(xo8));
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) oaa8 <= a_gt_b7 ? oa7 : ob7;
|
if (ce) oaa8 <= a_gt_b7 ? oa7 : ob7;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) obb8 <= a_gt_b7 ? ob7 : oa7;
|
if (ce) obb8 <= a_gt_b7 ? ob7 : oa7;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock edge #9
|
// Clock edge #9
|
// perform add/subtract
|
// perform add/subtract
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
reg [FMSB+4:0] mab9;
|
reg [FMSB+4:0] mab9;
|
wire anbInf9;
|
wire anbInf9;
|
wire aNan9, bNan9;
|
wire aNan9, bNan9;
|
wire op9;
|
wire op9;
|
wire [FMSB+1:0] fracta9, fractb9;
|
wire [FMSB+1:0] fracta9, fractb9;
|
wire xo9;
|
wire xo9;
|
reg xinf9;
|
reg xinf9;
|
|
|
vtdl #(1) danbInf7(.clk(clk), .ce(ce), .a(4'd6), .d(anbInf2), .q(anbInf9));
|
vtdl #(1) danbInf7(.clk(clk), .ce(ce), .a(4'd6), .d(anbInf2), .q(anbInf9));
|
vtdl #(1) danan8(.clk(clk), .ce(ce), .a(4'd7), .d(aNan1), .q(aNan9));
|
vtdl #(1) danan8(.clk(clk), .ce(ce), .a(4'd7), .d(aNan1), .q(aNan9));
|
vtdl #(1) dbnan8(.clk(clk), .ce(ce), .a(4'd7), .d(bNan1), .q(bNan9));
|
vtdl #(1) dbnan8(.clk(clk), .ce(ce), .a(4'd7), .d(bNan1), .q(bNan9));
|
vtdl #(1) dop6(.clk(clk), .ce(ce), .a(4'd5), .d(op3), .q(op9));
|
vtdl #(1) dop6(.clk(clk), .ce(ce), .a(4'd5), .d(op3), .q(op9));
|
delay3 #(FMSB+2) dfracta8(.clk(clk), .ce(ce), .i(fracta6), .o(fracta9) );
|
delay3 #(FMSB+2) dfracta8(.clk(clk), .ce(ce), .i(fracta6), .o(fracta9) );
|
delay3 #(FMSB+2) dfractb8(.clk(clk), .ce(ce), .i(fractb6), .o(fractb9) );
|
delay3 #(FMSB+2) dfractb8(.clk(clk), .ce(ce), .i(fractb6), .o(fractb9) );
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) mab9 <= realOp8 ? oaa8 - obb8 : oaa8 + obb8;
|
if (ce) mab9 <= realOp8 ? oaa8 - obb8 : oaa8 + obb8;
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) xinf9 <= xo8 == {EMSB+1{1'b1}};
|
if (ce) xinf9 <= xo8 == {EMSB+1{1'b1}};
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Clock edge #10
|
// Clock edge #10
|
// Final outputs
|
// Final outputs
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
vtdl #(1) dso6(.clk(clk), .ce(ce), .a(4'd5), .d(so4), .q(so));
|
vtdl #(1) dso6(.clk(clk), .ce(ce), .a(4'd5), .d(so4), .q(so));
|
vtdl #(.WID(EMSB+1)) dxo6(.clk(clk), .ce(ce), .a(4'd1), .d(xo8), .q(xo));
|
vtdl #(.WID(EMSB+1)) dxo6(.clk(clk), .ce(ce), .a(4'd1), .d(xo8), .q(xo));
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce)
|
if (ce)
|
casez({anbInf9,aNan9,bNan9,xinf9})
|
casez({anbInf9,aNan9,bNan9,xinf9})
|
4'b1???: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
|
4'b1???: mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
|
4'b01??: mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}}; // set MSB of Nan to convert to quiet
|
4'b01??: mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}}; // Set MSB of Nan to convert to quiet
|
4'b001?: mo <= {1'b1,1'b1,fractb9[FMSB-1:0],{FMSB+1{1'b0}}};
|
4'b001?: mo <= {1'b1,1'b1,fractb9[FMSB-1:0],{FMSB+1{1'b0}}};
|
4'b0001: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero
|
4'b0001: mo <= 1'd0; // exponent hit infinity -> force mantissa to zero
|
default: mo <= {mab9,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
|
default: mo <= {mab9,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
module fpAddsubnr(clk, ce, rm, op, a, b, o);
|
module fpAddsubnr(clk, ce, rm, op, a, b, o);
|
parameter FPWID = 128;
|
parameter FPWID = 128;
|
`include "fpSize.sv"
|
`include "fpSize.sv"
|
|
|
input clk; // system clock
|
input clk; // system clock
|
input ce; // core clock enable
|
input ce; // core clock enable
|
input [2:0] rm; // rounding mode
|
input [2:0] rm; // rounding mode
|
input op; // operation 0 = add, 1 = subtract
|
input op; // operation 0 = add, 1 = subtract
|
input [MSB:0] a; // operand a
|
input [MSB:0] a; // operand a
|
input [MSB:0] b; // operand b
|
input [MSB:0] b; // operand b
|
output [MSB:0] o; // output
|
output [MSB:0] o; // output
|
|
|
wire [EX:0] o1;
|
wire [EX:0] o1;
|
wire [MSB+3:0] fpn0;
|
wire [MSB+3:0] fpn0;
|
|
|
fpAddsub #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
|
fpAddsub #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
|
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
|
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
|
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
|
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
|
|
|
endmodule
|
endmodule
|
|
|
