// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
|
// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@finitron.ca
|
// \/_// robfinch<remove>@finitron.ca
|
// ||
|
// ||
|
//
|
//
|
// fpSqrt.v
|
// fpSqrt.v
|
// - floating point square root
|
// - floating point square root
|
// - parameterized width
|
// - parameterized width
|
// - IEEE 754 representation
|
// - IEEE 754 representation
|
//
|
//
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
// it under the terms of the GNU Lesser General Public License as published
|
// it under the terms of the GNU Lesser General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or
|
// by the Free Software Foundation, either version 3 of the License, or
|
// (at your option) any later version.
|
// (at your option) any later version.
|
//
|
//
|
// This source file is distributed in the hope that it will be useful,
|
// This source file is distributed in the hope that it will be useful,
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// Floating Point Multiplier / Divider
|
// Floating Point Multiplier / Divider
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
|
|
`include "fpConfig.sv"
|
`include "fpConfig.sv"
|
`include "fp_defines.v"
|
`include "fp_defines.v"
|
|
|
module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
|
module fpSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
|
parameter FPWID = 32;
|
parameter FPWID = 32;
|
`include "fpSize.sv"
|
`include "fpSize.sv"
|
localparam pShiftAmt =
|
localparam pShiftAmt =
|
FPWID==80 ? 48 :
|
FPWID==80 ? 48 :
|
FPWID==64 ? 36 :
|
FPWID==64 ? 36 :
|
FPWID==32 ? 7 : (FMSB+1-16);
|
FPWID==32 ? 7 : (FMSB+1-16);
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
input ce;
|
input ce;
|
input ld;
|
input ld;
|
input [MSB:0] a;
|
input [MSB:0] a;
|
output reg [EX:0] o;
|
output reg [EX:0] o;
|
output done;
|
output done;
|
output sqrinf;
|
output sqrinf;
|
output sqrneg;
|
output sqrneg;
|
|
|
// registered outputs
|
// registered outputs
|
reg sign_exe;
|
reg sign_exe;
|
reg inf;
|
reg inf;
|
reg overflow;
|
reg overflow;
|
reg underflow;
|
reg underflow;
|
|
|
wire so;
|
wire so;
|
wire [EMSB:0] xo;
|
wire [EMSB:0] xo;
|
wire [FX:0] mo;
|
wire [FX:0] mo;
|
|
|
// constants
|
// constants
|
wire [EMSB:0] infXp = {EMSB+1{1'b1}}; // infinite / NaN - all ones
|
wire [EMSB:0] infXp = {EMSB+1{1'b1}}; // infinite / NaN - all ones
|
// The following is the value for an exponent of zero, with the offset
|
// The following is the value for an exponent of zero, with the offset
|
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
|
// eg. 8'h7f for eight bit exponent, 11'h7ff for eleven bit exponent, etc.
|
wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}}; //2^0 exponent
|
wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}}; //2^0 exponent
|
// The following is a template for a quiet nan. (MSB=1)
|
// The following is a template for a quiet nan. (MSB=1)
|
wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
|
wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
|
|
|
// variables
|
// variables
|
wire [EMSB+2:0] ex1; // sum of exponents
|
wire [EMSB+2:0] ex1; // sum of exponents
|
wire [FX:0] sqrto;
|
wire [FX:0] sqrto;
|
|
|
// Operands
|
// Operands
|
wire sa; // sign bit
|
wire sa; // sign bit
|
wire [EMSB:0] xa; // exponent bits
|
wire [EMSB:0] xa; // exponent bits
|
wire [FMSB+1:0] fracta;
|
wire [FMSB+1:0] fracta;
|
wire a_dn; // a/b is denormalized
|
wire a_dn; // a/b is denormalized
|
wire az;
|
wire az;
|
wire aInf;
|
wire aInf;
|
wire aNan;
|
wire aNan;
|
wire done1;
|
wire done1;
|
wire [7:0] lzcnt;
|
wire [7:0] lzcnt;
|
wire [MSB:0] aa;
|
wire [MSB:0] aa;
|
|
|
// -----------------------------------------------------------
|
// -----------------------------------------------------------
|
// - decode the input operand
|
// - decode the input operand
|
// - derive basic information
|
// - derive basic information
|
// - calculate exponent
|
// - calculate exponent
|
// - calculate fraction
|
// - calculate fraction
|
// -----------------------------------------------------------
|
// -----------------------------------------------------------
|
|
|
fpDecompReg #(FPWID) u1
|
fpDecompReg #(FPWID) u1
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.ce(ce),
|
.ce(ce),
|
.i(a),
|
.i(a),
|
.o(aa),
|
.o(aa),
|
.sgn(sa),
|
.sgn(sa),
|
.exp(xa),
|
.exp(xa),
|
.fract(fracta),
|
.fract(fracta),
|
.xz(a_dn),
|
.xz(a_dn),
|
.vz(az),
|
.vz(az),
|
.inf(aInf),
|
.inf(aInf),
|
.nan(aNan)
|
.nan(aNan)
|
);
|
);
|
|
|
assign ex1 = xa + 8'd1;
|
assign ex1 = xa + 8'd1;
|
assign so = 1'b0; // square root of positive numbers only
|
assign so = 1'b0; // square root of positive numbers only
|
assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
|
assign xo = (ex1 >> 1) + (bias >> 1); // divide by 2 cuts the bias in half, so 1/2 of it is added back in.
|
assign mo = aNan ? {1'b1,aa[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << pShiftAmt);
|
assign mo = aNan ? {1'b1,aa[FMSB:0],{FMSB+1{1'b0}}} : (sqrto << pShiftAmt);
|
assign sqrinf = aInf;
|
assign sqrinf = aInf;
|
assign sqrneg = !az & so;
|
assign sqrneg = !az & so;
|
|
|
wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
|
wire [FMSB+2:0] fracta1 = ex1[0] ? {1'b0,fracta} << 1 : {2'b0,fracta};
|
|
|
wire ldd;
|
wire ldd;
|
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(ld), .o(ldd));
|
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(ld), .o(ldd));
|
|
|
isqrt #(FX+1) u2
|
isqrt #(FX+1) u2
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.ce(ce),
|
.ce(ce),
|
.ld(ldd),
|
.ld(ldd),
|
.a({1'b0,fracta1,{FMSB+1{1'b0}}}),
|
.a({1'b0,fracta1,{FMSB+1{1'b0}}}),
|
.o(sqrto),
|
.o(sqrto),
|
.done(done)
|
.done(done)
|
);
|
);
|
|
|
always @*
|
always @*
|
casez({aNan,sqrinf,sqrneg})
|
casez({aNan,sqrinf,sqrneg})
|
3'b1??: o <= {sa,xa,mo};
|
3'b1??: o <= {sa,xa,mo};
|
3'b01?: o <= {sa,1'b1,qNaN|`QSQRTINF,{FMSB+1{1'b0}}};
|
3'b01?: o <= {sa,1'b1,qNaN|`QSQRTINF,{FMSB+1{1'b0}}};
|
3'b001: o <= {sa,1'b1,qNaN|`QSQRTNEG,{FMSB+1{1'b0}}};
|
3'b001: o <= {sa,1'b1,qNaN|`QSQRTNEG,{FMSB+1{1'b0}}};
|
default: o <= {so,xo,mo};
|
default: o <= {so,xo,mo};
|
endcase
|
endcase
|
|
|
|
|
endmodule
|
endmodule
|
|
|
module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
|
module fpSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
|
parameter FPWID=32;
|
parameter FPWID=32;
|
`include "fpSize.sv"
|
`include "fpSize.sv"
|
|
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
input ce;
|
input ce;
|
input ld;
|
input ld;
|
input [MSB:0] a;
|
input [MSB:0] a;
|
output [MSB:0] o;
|
output [MSB:0] o;
|
input [2:0] rm;
|
input [2:0] rm;
|
output done;
|
output done;
|
output inf;
|
output inf;
|
output sqrinf;
|
output sqrinf;
|
output sqrneg;
|
output sqrneg;
|
|
|
wire [EX:0] o1;
|
wire [EX:0] o1;
|
wire inf1;
|
wire inf1;
|
wire [MSB+3:0] fpn0;
|
wire [MSB+3:0] fpn0;
|
wire done1;
|
wire done1;
|
|
|
fpSqrt #(FPWID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
|
fpSqrt #(FPWID) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
|
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
|
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
|
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
|
fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
|
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
|
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
|
delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
|
vtdl #(1) u8(.clk(clk), .ce(ce), .a(4'd10), .d(done1), .q(done));
|
endmodule
|
endmodule
|
|
|
|
|