// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2022 Robert Finch, Waterloo
|
// \\__/ o\ (C) 2022 Robert Finch, Waterloo
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch@finitron.ca
|
// \/_// robfinch@finitron.ca
|
// ||
|
// ||
|
//
|
//
|
// i2df128.sv
|
// i2df128.sv
|
// - convert integer to decimal floating point
|
// - convert integer to decimal floating point
|
//
|
//
|
// BSD 3-Clause License
|
// BSD 3-Clause License
|
// Redistribution and use in source and binary forms, with or without
|
// Redistribution and use in source and binary forms, with or without
|
// modification, are permitted provided that the following conditions are met:
|
// modification, are permitted provided that the following conditions are met:
|
//
|
//
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
// list of conditions and the following disclaimer.
|
// list of conditions and the following disclaimer.
|
//
|
//
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
// this list of conditions and the following disclaimer in the documentation
|
// this list of conditions and the following disclaimer in the documentation
|
// and/or other materials provided with the distribution.
|
// and/or other materials provided with the distribution.
|
//
|
//
|
// 3. Neither the name of the copyright holder nor the names of its
|
// 3. Neither the name of the copyright holder nor the names of its
|
// contributors may be used to endorse or promote products derived from
|
// contributors may be used to endorse or promote products derived from
|
// this software without specific prior written permission.
|
// this software without specific prior written permission.
|
//
|
//
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
|
|
import DFPPkg::*;
|
import DFPPkg::*;
|
|
|
module i2df128 (rst, clk, ce, ld, op, rm, i, o, done);
|
module i2df128 (rst, clk, ce, ld, op, rm, i, o, done);
|
parameter FPWID=128;
|
parameter FPWID=128;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
input ce;
|
input ce;
|
input ld;
|
input ld;
|
input op; // 1 = signed, 0 = unsigned
|
input op; // 1 = signed, 0 = unsigned
|
input [2:0] rm; // rounding mode
|
input [2:0] rm; // rounding mode
|
input [127:0] i; // integer input
|
input [127:0] i; // integer input
|
output [127:0] o; // float output
|
output [127:0] o; // float output
|
output done;
|
output done;
|
|
|
wire [127:0] i1 = (op & i[127]) ? -i : i;
|
wire [127:0] i1 = (op & i[127]) ? -i : i;
|
wire [171:0] bcd;
|
wire [171:0] bcd;
|
wire done1, done2;
|
wire done1, done2;
|
assign done = done1 & done2;
|
assign done = done1 & done2;
|
|
|
DDBinToBCD ub2b1
|
DDBinToBCD ub2b1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(clk),
|
.clk(clk),
|
.ld(ld),
|
.ld(ld),
|
.bin(i1),
|
.bin(i1),
|
.bcd(bcd),
|
.bcd(bcd),
|
.done(done1)
|
.done(done1)
|
);
|
);
|
|
|
DFP128U ui;
|
DFP128U ui;
|
wire [13:0] zeroXp = {13{1'b1}};
|
wire [13:0] zeroXp = 14'h17FF;
|
|
|
reg iz; // zero input ?
|
reg iz; // zero input ?
|
wire [7:0] lz; // count the leading zeros in the number
|
wire [7:0] lz; // count the leading zeros in the number
|
reg [7:0] lz4; // leading zero rounded to multiple of four
|
reg [7:0] lz4; // leading zero rounded to multiple of four
|
wire [13:0] wd; // compute number of whole digits
|
wire [13:0] wd; // compute number of whole digits
|
reg so; // copy the sign of the input (easy)
|
reg so; // copy the sign of the input (easy)
|
reg [2:0] rmd;
|
reg [2:0] rmd;
|
wire [171:0] bcd1;
|
wire [171:0] bcd1;
|
reg [135:0] simag;
|
reg [135:0] simag;
|
|
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
rmd <= rm;
|
rmd <= rm;
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
iz <= i==0;
|
iz <= i==0;
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
so <= i[127];
|
so <= i[127];
|
|
|
delay1 #(172) u2 (.clk(clk), .ce(ce), .i(bcd), .o(bcd1) );
|
delay1 #(172) u2 (.clk(clk), .ce(ce), .i(bcd), .o(bcd1) );
|
cntlz192Reg u4 (.clk(clk), .ce(ce), .i({bcd,20'd0}), .o(lz) );
|
cntlz192Reg u4 (.clk(clk), .ce(ce), .i({bcd,20'd0}), .o(lz) );
|
|
|
always_comb
|
always_comb
|
lz4 = lz >> 2'd2;
|
lz4 = lz >> 2'd2;
|
|
|
assign wd = zeroXp - 8'd1 + 8'd34 - lz4 + 8'd9; // constant except for lz
|
assign wd = zeroXp - 8'd1 + 8'd34 - lz4 + 8'd9; // constant except for lz
|
|
|
reg [13:0] xo;
|
reg [13:0] xo;
|
|
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
xo <= iz ? 'd0 : wd;
|
xo <= iz ? 'd0 : wd;
|
|
|
// left align number
|
// left align number
|
// The number may to too large to represent entirely precisely in which case a
|
// The number may to too large to represent entirely precisely in which case a
|
// right shift is required. There are only about 114 bits of precision, but the
|
// right shift is required. There are only about 114 bits of precision, but the
|
// incoming number is allowed to be 128-bit.
|
// incoming number is allowed to be 128-bit.
|
// Rounding is required only when the number needs to be right-shifted.
|
// Rounding is required only when the number needs to be right-shifted.
|
|
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
if (lz4 < 8'd9)
|
if (lz4 < 8'd9)
|
simag = bcd1 >> {8'd9 - lz4,2'd0};
|
simag = bcd1 >> {8'd9 - lz4,2'd0};
|
else
|
else
|
simag = bcd1 << {lz4 - 8'd9,2'd0};
|
simag = bcd1 << {lz4 - 8'd9,2'd0};
|
|
|
wire g = bcd1[{8'd9 - lz4,2'd0}]; // guard bit (lsb)
|
wire g = bcd1[{8'd9 - lz4,2'd0}]; // guard bit (lsb)
|
wire r = bcd1[{8'd9 - lz4,2'd0}-1]; // rounding bit
|
wire r = bcd1[{8'd9 - lz4,2'd0}-1]; // rounding bit
|
wire s = |(bcd1 & (172'd1 << {8'd9 - lz4,2'd0}-2) - 2'd1); // "sticky" bit
|
wire s = |(bcd1 & (172'd1 << {8'd9 - lz4,2'd0}-2) - 2'd1); // "sticky" bit
|
reg rnd;
|
reg rnd;
|
|
|
// Compute the round bit
|
// Compute the round bit
|
always_ff @(posedge clk)
|
always_ff @(posedge clk)
|
if (lz4 < 8'd9)
|
if (lz4 < 8'd9)
|
case (rmd)
|
case (rmd)
|
3'd0: rnd = (g & r) | (r & s); // round to nearest even
|
3'd0: rnd = (g & r) | (r & s); // round to nearest even
|
3'd1: rnd = 0; // round to zero (truncate)
|
3'd1: rnd = 0; // round to zero (truncate)
|
3'd2: rnd = (r | s) & !so; // round towards +infinity
|
3'd2: rnd = (r | s) & !so; // round towards +infinity
|
3'd3: rnd = (r | s) & so; // round towards -infinity
|
3'd3: rnd = (r | s) & so; // round towards -infinity
|
3'd4: rnd = (r | s);
|
3'd4: rnd = (r | s);
|
default: rnd = (g & r) | (r & s); // round to nearest even
|
default: rnd = (g & r) | (r & s); // round to nearest even
|
endcase
|
endcase
|
else
|
else
|
rnd = 1'b0;
|
rnd = 1'b0;
|
|
|
// round the result
|
// round the result
|
assign ui.sig = simag[135:0] + rnd;
|
assign ui.sig = simag[135:0] + rnd;
|
assign ui.exp = xo[13:0];
|
assign ui.exp = xo[13:0];
|
assign ui.sign = op & so;
|
assign ui.sign = op & so;
|
assign ui.nan = 1'b0;
|
assign ui.nan = 1'b0;
|
assign ui.qnan = 1'b0;
|
assign ui.qnan = 1'b0;
|
assign ui.snan = 1'b0;
|
assign ui.snan = 1'b0;
|
assign ui.infinity = 1'b0;
|
assign ui.infinity = 1'b0;
|
|
|
DFPPack128 upk1 (ui, o);
|
DFPPack128 upk1 (ui, o);
|
|
|
ft_delay #(.WID(1), .DEP(4)) udly1 (.clk(clk), .ce(1'b1), .i(done1), .o(done2));
|
ft_delay #(.WID(1), .DEP(4)) udly1 (.clk(clk), .ce(1'b1), .i(done1), .o(done2));
|
|
|
endmodule
|
endmodule
|
|
|
