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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2010-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2010-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// isqrt.v
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// isqrt.v
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// - integer square root
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// - integer square root
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// - uses the standard long form calc.
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// - uses the standard long form calc.
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// - geared towards use in an floating point unit
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// - geared towards use in an floating point unit
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// - calculates to FPWID fractional precision (double FPWIDth output)
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// - calculates to WID fractional precision (double width output)
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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module isqrt(rst, clk, ce, ld, a, o, done);
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module isqrt(rst, clk, ce, ld, a, o, done);
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parameter FPWID = 32;
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parameter WID = 32;
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localparam MSB = FPWID-1;
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localparam MSB = WID-1;
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parameter IDLE=3'd0;
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parameter IDLE=3'd0;
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parameter CALC=3'd1;
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parameter CALC=3'd1;
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parameter DONE=3'd2;
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parameter DONE=3'd2;
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input rst;
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input rst;
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input clk;
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input clk;
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input ce;
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input ce;
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input ld;
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input ld;
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input [MSB:0] a;
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input [MSB:0] a;
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output [FPWID*2-1:0] o;
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output [WID*2-1:0] o;
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output done;
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output done;
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reg [2:0] state;
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reg [2:0] state;
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reg [FPWID*2:0] root;
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reg [WID*2:0] root;
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wire [FPWID*2-1:0] testDiv;
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wire [WID*2-1:0] testDiv;
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reg [FPWID*2-1:0] remLo;
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reg [WID*2-1:0] remLo;
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reg [FPWID*2-1:0] remHi;
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reg [WID*2-1:0] remHi;
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wire cnt_done;
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wire cnt_done;
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assign testDiv = {root[FPWID*2-2:0],1'b1};
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assign testDiv = {root[WID*2-2:0],1'b1};
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wire [FPWID*2-1:0] remHiShift = {remHi[FPWID*2-3:0],remLo[FPWID*2-1:FPWID*2-2]};
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wire [WID*2-1:0] remHiShift = {remHi[WID*2-3:0],remLo[WID*2-1:WID*2-2]};
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wire doesGoInto = remHiShift >= testDiv;
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wire doesGoInto = remHiShift >= testDiv;
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assign o = root[FPWID*2:1];
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assign o = root[WID*2:1];
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// Iteration counter
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// Iteration counter
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reg [7:0] cnt;
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reg [7:0] cnt;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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cnt <= FPWID*2;
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cnt <= WID*2;
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remLo <= {FPWID*2{1'b0}};
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remLo <= {WID*2{1'b0}};
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remHi <= {FPWID*2{1'b0}};
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remHi <= {WID*2{1'b0}};
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root <= {FPWID*2+1{1'b0}};
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root <= {WID*2+1{1'b0}};
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state <= IDLE;
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state <= IDLE;
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end
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end
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else if (ce) begin
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else
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begin
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if (ce) begin
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if (!cnt_done)
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if (!cnt_done)
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cnt <= cnt + 8'd1;
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cnt <= cnt + 8'd1;
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case(state)
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case(state)
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IDLE:
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IDLE: ;
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if (ld) begin
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cnt <= 8'd0;
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state <= CALC;
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remLo <= {a,32'h0};
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remHi <= {FPWID*2{1'b0}};
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root <= {FPWID*2+1{1'b0}};
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end
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CALC:
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CALC:
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if (!cnt_done) begin
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if (!cnt_done) begin
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// Shift the remainder low
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// Shift the remainder low
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remLo <= {remLo[FPWID*2-3:0],2'd0};
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remLo <= {remLo[WID*2-3:0],2'd0};
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// Shift the remainder high
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// Shift the remainder high
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remHi <= doesGoInto ? remHiShift - testDiv: remHiShift;
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remHi <= doesGoInto ? remHiShift - testDiv: remHiShift;
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// Shift the root
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// Shift the root
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root <= {root+doesGoInto,1'b0}; // root * 2 + 1/0
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root <= {root+doesGoInto,1'b0}; // root * 2 + 1/0
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end
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end
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else begin
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else begin
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cnt <= 8'h00;
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cnt <= 8'h00;
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state <= DONE;
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state <= DONE;
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end
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end
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DONE:
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DONE:
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begin
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begin
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cnt <= cnt + 8'd1;
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cnt <= cnt + 8'd1;
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if (cnt == 8'd6)
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if (cnt == 8'd6)
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state <= IDLE;
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state <= IDLE;
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end
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end
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default: state <= IDLE;
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endcase
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endcase
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if (ld) begin
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cnt <= 8'd0;
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state <= CALC;
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remLo <= {a,32'd0};
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remHi <= {WID*2{1'b0}};
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root <= {WID*2+1{1'b0}};
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end
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end
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end
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end
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assign cnt_done = (cnt==FPWID);
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assign cnt_done = (cnt==WID);
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assign done = state==DONE;
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assign done = state==DONE;
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endmodule
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endmodule
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module isqrt_tb();
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module isqrt_tb();
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reg clk;
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reg clk;
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reg rst;
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reg rst;
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reg [31:0] a;
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reg [31:0] a;
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wire [63:0] o;
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wire [63:0] o;
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reg ld;
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reg ld;
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wire done;
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wire done;
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reg [7:0] state;
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reg [7:0] state;
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initial begin
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initial begin
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clk = 1;
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clk = 1;
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rst = 0;
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rst = 0;
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#100 rst = 1;
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#100 rst = 1;
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#100 rst = 0;
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#100 rst = 0;
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end
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end
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always #10 clk = ~clk; // 50 MHz
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always #10 clk = ~clk; // 50 MHz
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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state <= 8'd0;
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state <= 8'd0;
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a <= 32'h912345;
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a <= 32'h912345;
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end
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end
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else
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else
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begin
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begin
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ld <= 1'b0;
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ld <= 1'b0;
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case(state)
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case(state)
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8'd0:
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8'd0:
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begin
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begin
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a <= 32'h9123456;
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a <= 32'h9123456;
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ld <= 1'b1;
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ld <= 1'b1;
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state <= 8'd1;
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state <= 8'd1;
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end
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end
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8'd1:
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8'd1:
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if (done) begin
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if (done) begin
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$display("i=%h o=%h", a, o);
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$display("i=%h o=%h", a, o);
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end
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end
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endcase
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endcase
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end
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end
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isqrt #(32) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(ld), .a(a), .o(o), .done(done));
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isqrt #(32) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(ld), .a(a), .o(o), .done(done));
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endmodule
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endmodule
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