// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// mult128x128.sv
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// mult128x128.sv
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// - Karatsuba multiply
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// - Karatsuba multiply
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// - 15 cycle latency
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// - 15 cycle latency
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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//`define KARATSUBA 1
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`ifdef KARATSUBA
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module mult128x128(clk, ce, a, b, o);
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module mult128x128(clk, ce, a, b, o);
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input clk;
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input clk;
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input ce;
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input ce;
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input [127:0] a;
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input [127:0] a;
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input [127:0] b;
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input [127:0] b;
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output reg [255:0] o;
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output reg [255:0] o;
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reg [63:0] a2, b2;
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reg [63:0] a2, b2;
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reg [64:0] a1, b1;
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reg [64:0] a1, b1;
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reg [127:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4;
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reg [127:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4;
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reg [128:0] z1; // extra bit for carry
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reg [128:0] z1; // extra bit for carry
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reg sgn2, sgn10;
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reg sgn2, sgn10;
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wire sgn9;
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wire sgn9;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) a1 <= a[63: 0] - a[127:64]; // x0-x1
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if (ce) a1 <= a[63: 0] - a[127:64]; // x0-x1
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always @(posedge clk)
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always @(posedge clk)
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if (ce) b1 <= b[127:64] - b[63: 0]; // y1-y0
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if (ce) b1 <= b[127:64] - b[63: 0]; // y1-y0
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always @(posedge clk)
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always @(posedge clk)
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if (ce) a2 <= a1[64] ? -a1 : a1;
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if (ce) a2 <= a1[64] ? -a1 : a1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) b2 <= b1[64] ? -b1 : b1;
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if (ce) b2 <= b1[64] ? -b1 : b1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sgn2 <= a1[64]^b1[64];
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if (ce) sgn2 <= a1[64]^b1[64];
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delay #(.WID(1), .DEP(12)) udl1 (.clk(clk), .ce(ce), .i(sgn2), .o(sgn9));
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ft_delay #(.WID(1), .DEP(12)) udl1 (.clk(clk), .ce(ce), .i(sgn2), .o(sgn9));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sgn10 <= sgn9;
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if (ce) sgn10 <= sgn9;
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// 11 cycle latency
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// 11 cycle latency
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mult64x64 u1 (
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mult64x64 u1 (
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.clk(clk),
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.clk(clk),
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.ce(ce),
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.ce(ce),
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.a(a[127:64]),
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.a(a[127:64]),
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.b(b[127:64]),
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.b(b[127:64]),
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.o(z2) // z2 = x1 * y1
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.o(z2) // z2 = x1 * y1
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);
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);
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mult64x64 u2 (
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mult64x64 u2 (
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.clk(clk),
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.clk(clk),
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.ce(ce),
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.ce(ce),
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.a(a[63:0]),
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.a(a[63:0]),
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.b(b[63:0]),
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.b(b[63:0]),
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.o(z0) // z0 = x0 * y0
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.o(z0) // z0 = x0 * y0
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);
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);
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mult64x64 u3 (
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mult64x64 u3 (
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.clk(clk),
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.clk(clk),
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.ce(ce),
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.ce(ce),
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.a(a2[63:0]),
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.a(a2[63:0]),
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.b(b2[63:0]),
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.b(b2[63:0]),
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.o(p3) // p3 = abs(x0-x1) * abs(y1-y0)
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.o(p3) // p3 = abs(x0-x1) * abs(y1-y0)
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);
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);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) p4 <= sgn9 ? -p3 : p3;
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if (ce) p4 <= sgn9 ? -p3 : p3;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z2a <= z2;
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if (ce) z2a <= z2;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z0a <= z0;
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if (ce) z0a <= z0;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z2b <= z2a;
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if (ce) z2b <= z2a;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z0b <= z0a;
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if (ce) z0b <= z0a;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z2c <= z2b;
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if (ce) z2c <= z2b;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z0c <= z0b;
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if (ce) z0c <= z0b;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z1 <= {{128{sgn10}},p4} + z2c + z0c;
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if (ce) z1 <= {{128{sgn10}},p4} + z2c + z0c;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z2d <= z2c;
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if (ce) z2d <= z2c;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) z0d <= z0c;
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if (ce) z0d <= z0c;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) o <= {z2d,z0d} + {z1,64'd0};
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if (ce) o <= {z2d,z0d} + {z1,64'd0};
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endmodule
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endmodule
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`else
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// This version of the multiply has a parameterized pipeline depth and allows
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// the tools to perform the multiply. Relies on the ability of tools to retime.
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module mult128x128(clk, ce, a, b, o);
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parameter DEP = 18;
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input clk;
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input ce;
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input [127:0] a;
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input [127:0] b;
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output reg [255:0] o;
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reg [255:0] prod [0:DEP-1];
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reg [255:0] prd;
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integer n;
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always_ff @(posedge clk)
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if (ce) prd <= a * b;
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always_ff @(posedge clk)
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if (ce) prod[0] <= prd;
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always_ff @(posedge clk)
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for (n = 0; n < DEP - 1; n = n + 1)
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if (ce) prod[n+1] <= prod[n];
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always_ff @(posedge clk)
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if(ce) o <= prod[DEP-1];
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endmodule
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`endif
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