`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// DFPAddsub_tb.v
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// DFPAddsub_tb.v
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// - decimal floating point addsub test bench
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// - decimal floating point addsub test bench
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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module DFPAddsub_tb();
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module DFPAddsub_tb();
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reg rst;
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reg rst;
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reg clk;
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reg clk;
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reg [15:0] adr;
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reg [15:0] adr;
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reg [127:0] a,b;
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reg [151:0] a,b;
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wire [127:0] o;
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wire [151:0] o;
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reg [127:0] ad,bd;
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reg [151:0] ad,bd;
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reg [127:0] od;
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reg [151:0] od;
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reg [3:0] rm;
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reg [3:0] rm;
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integer n;
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integer n;
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reg [127:0] a1, b1;
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reg [151:0] a1, b1;
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wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
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wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
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wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
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wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
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integer outfile;
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integer outfile;
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initial begin
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initial begin
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rst = 1'b0;
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rst = 1'b0;
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clk = 1'b0;
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clk = 1'b0;
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adr = 0;
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adr = 0;
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a = $urandom(1);
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a = $urandom(1);
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b = 1;
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b = 1;
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#20 rst = 1;
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#20 rst = 1;
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#50 rst = 0;
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#50 rst = 0;
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#10000000 $fclose(outfile);
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#10000000 $fclose(outfile);
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#10 $finish;
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#10 $finish;
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end
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end
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always #5
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always #5
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clk = ~clk;
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clk = ~clk;
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genvar g;
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genvar g;
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generate begin : gRand
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generate begin : gRand
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for (g = 0; g < 128; g = g + 4) begin
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for (g = 0; g < 152; g = g + 4) begin
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always @(posedge clk) begin
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always @(posedge clk) begin
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a1[g+3:g] <= $urandom() % 10;
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a1[g+3:g] <= $urandom() % 10;
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b1[g+3:g] <= $urandom() % 10;
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b1[g+3:g] <= $urandom() % 10;
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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reg [7:0] count;
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reg [7:0] count;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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adr <= 0;
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adr <= 0;
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count <= 0;
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count <= 0;
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end
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end
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else
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else
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begin
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begin
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if (adr==0) begin
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if (adr==0) begin
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outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPAddsub_tvo.txt", "wb");
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outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPAddsub_tvo.txt", "wb");
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$fwrite(outfile, " rm ------- A ------ ------- B ------ ------ sum ----- -- SIM Sum --\n");
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$fwrite(outfile, " rm ------- A ------ ------- B ------ ------ sum ----- -- SIM Sum --\n");
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end
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end
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count <= count + 1;
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count <= count + 1;
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if (count > 32)
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if (count > 32)
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count <= 1'd1;
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count <= 1'd1;
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if (count==2) begin
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if (count==2) begin
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a[127:0] <= a1;
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a <= a1;
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b[127:0] <= b1;
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b <= b1;
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a[127:124] <= 4'h5;
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a[151:148] <= 4'h5;
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b[127:124] <= 4'h5;
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b[151:148] <= 4'h5;
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rm <= adr[14:12];
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rm <= adr[14:12];
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//ad <= memd[adr][63: 0];
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//ad <= memd[adr][63: 0];
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//bd <= memd[adr][127:64];
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//bd <= memd[adr][127:64];
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end
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end
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if (adr==1 && count==2) begin
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if (adr==1 && count==2) begin
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a <= 127'h50000700000000000000000000000000;
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a <= 152'h50000700000000000000000000000000000000;
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b <= 127'h50000200000000000000000000000000;
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b <= 152'h50000200000000000000000000000000000000;
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end
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end
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if (adr==2 && count==2) begin
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if (adr==2 && count==2) begin
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a <= 127'h50000900000000000000000000000000;
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a <= 152'h50000900000000000000000000000000000000;
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b <= 127'h50000200000000000000000000000000;
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b <= 152'h50000200000000000000000000000000000000;
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end
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end
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if (adr==3 && count==2) begin
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if (adr==3 && count==2) begin
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a <= 127'h50000000000000000000000000000000;
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a <= 152'h50000000000000000000000000000000000000;
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b <= 127'h50000000000000000000000000000000;
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b <= 152'h50000000000000000000000000000000000000;
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end
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end
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if (count==31) begin
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if (count==31) begin
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if (adr[11]) begin
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if (adr[11]) begin
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$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
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$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
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end
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end
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else begin
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else begin
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$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);
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$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);
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end
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end
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adr <= adr + 1;
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adr <= adr + 1;
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end
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end
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end
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end
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//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
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//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
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DFPAddsubnr u6 (
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DFPAddsubnr u6 (
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.clk(clk),
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.clk(clk),
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.ce(1'b1),
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.ce(1'b1),
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.op(adr[11]),
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.op(adr[11]),
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.a(a),
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.a(a),
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.b(b),
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.b(b),
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.o(o),
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.o(o),
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.rm(rm)
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.rm(rm)
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);
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);
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endmodule
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endmodule
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