`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// DFPMultiply_tb.v
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// DFPMultiply_tb.v
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// - decimal floating point multiplier test bench
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// - decimal floating point multiplier test bench
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Floating Point Multiplier / Divider
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// Floating Point Multiplier / Divider
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//
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//
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// This multiplier/divider handles denormalized numbers.
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// This multiplier/divider handles denormalized numbers.
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// The output format is of an internal expanded representation
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// The output format is of an internal expanded representation
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// in preparation to be fed into a normalization unit, then
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// in preparation to be fed into a normalization unit, then
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// rounding. Basically, it's the same as the regular format
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// rounding. Basically, it's the same as the regular format
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// except the mantissa is doubled in size, the leading two
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// except the mantissa is doubled in size, the leading two
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// bits of which are assumed to be whole bits.
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// bits of which are assumed to be whole bits.
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//
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//
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//
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//
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// ============================================================================
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// ============================================================================
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module DFPMultiply_tb();
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module DFPMultiply_tb();
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parameter N=33;
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reg rst;
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reg rst;
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reg clk;
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reg clk;
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reg [15:0] adr;
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reg [15:0] adr;
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reg [127:0] a,b;
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reg [N*4+16+4-1:0] a,b;
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wire [127:0] o;
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wire [N*4+16+4-1:0] o;
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reg [127:0] ad,bd;
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reg [N*4+16+4-1:0] ad,bd;
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wire [127:0] od;
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wire [N*4+16+4-1:0] od;
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reg [3:0] rm;
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reg [3:0] rm;
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integer n;
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integer n;
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reg [127:0] a1, b1;
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reg [127:0] a1, b1;
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wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
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wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
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wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
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wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
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wire done;
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wire done;
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reg ld;
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reg ld;
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integer outfile;
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integer outfile;
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initial begin
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initial begin
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rst = 1'b0;
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rst = 1'b0;
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clk = 1'b0;
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clk = 1'b0;
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adr = 0;
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adr = 0;
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a = $urandom(1);
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a = $urandom(1);
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#20 rst = 1;
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#20 rst = 1;
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#50 rst = 0;
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#50 rst = 0;
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#1000000 $fclose(outfile);
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#2000000 $fclose(outfile);
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#10 $finish;
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#10 $finish;
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end
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end
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always #5
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always #5
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clk = ~clk;
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clk = ~clk;
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genvar g;
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genvar g;
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generate begin : gRand
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generate begin : gRand
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for (g = 0; g < 128; g = g + 4) begin
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for (g = 0; g < N*4+16+4; g = g + 4) begin
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always @(posedge clk) begin
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always @(posedge clk) begin
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a1[g+3:g] <= $urandom() % 10;
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a1[g+3:g] <= $urandom() % 10;
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b1[g+3:g] <= $urandom() % 10;
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b1[g+3:g] <= $urandom() % 10;
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end
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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reg [9:0] count;
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reg [9:0] count;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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adr <= 0;
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adr <= 0;
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count <= 0;
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count <= 0;
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end
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end
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else
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else
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begin
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begin
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ld <= 1'b0;
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ld <= 1'b0;
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if (adr==0) begin
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if (adr==0) begin
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outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPMultiply_tvo.txt", "wb");
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outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPMultiply_tvo.txt", "wb");
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$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Product - - SIM Product -\n");
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$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Product - - SIM Product -\n");
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end
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end
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count <= count + 1;
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count <= count + 1;
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if (count > 600)
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if (count > 750)
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count <= 1'd1;
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count <= 1'd1;
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if (count==2) begin
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if (count==2) begin
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a[127:0] <= a1;
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a[N*4+16+4-1:0] <= a1;
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b[127:0] <= b1;
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b[N*4+16+4-1:0] <= b1;
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a[127:124] <= 4'h5;
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a[N*4+16+4-1:N*4+16+4-4] <= 4'h5;
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b[127:124] <= 4'h5;
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b[N*4+16+4-1:N*4+16+4-4] <= 4'h5;
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a[N*4+16+4-2] <= adr[7];
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a[N*4+16+4-3] <= adr[6];
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b[N*4+16+4-1] <= adr[5];
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b[N*4+16+4-4] <= adr[4];
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ld <= 1'b1;
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ld <= 1'b1;
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rm <= adr[15:13];
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rm <= adr[15:13];
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//ad <= memd[adr][63: 0];
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//ad <= memd[adr][63: 0];
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//bd <= memd[adr][127:64];
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//bd <= memd[adr][127:64];
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end
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end
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if (adr==1 && count==2) begin
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if (adr==1 && count==2) begin
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a <= 127'h50000700000000000000000000000000;
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a <= 152'h50000700000000000000000000000000000000;
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b <= 127'h50000200000000000000000000000000;
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b <= 152'h50000200000000000000000000000000000000;
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end
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end
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if (adr==1 && count==2) begin
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if (adr==1 && count==2) begin
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a <= 127'h40001333333333333333333333333333;
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a <= 152'h40001333333333333333333333333333333333;
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b <= 127'h50000300000000000000000000000000;
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b <= 152'h50000300000000000000000000000000000000;
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end
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end
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if (adr==2 && count==2) begin
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if (adr==2 && count==2) begin
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a <= 127'h50000900000000000000000000000000;
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a <= 152'h50000900000000000000000000000000000000;
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b <= 127'h50000200000000000000000000000000;
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b <= 152'h50000200000000000000000000000000000000;
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end
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end
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if (adr==3 && count==2) begin
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if (adr==3 && count==2) begin
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a <= 127'h50000000000000000000000000000000;
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a <= 152'h50000000000000000000000000000000000000;
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b <= 127'h50000000000000000000000000000000;
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b <= 152'h50000000000000000000000000000000000000;
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end
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end
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if (adr==4 && count==2) begin
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if (adr==4 && count==2) begin
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a <= 127'h50001100000000000000000000000000;
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a <= 152'h50001100000000000000000000000000000000;
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b <= 127'h50001100000000000000000000000000;
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b <= 152'h50001100000000000000000000000000000000;
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end
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end
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if (count==600) begin
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if (count==750) begin
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$fwrite(outfile, "%h\t%h\t%h\t%h\n", rm, a, b, o);
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$fwrite(outfile, "%h\t%h\t%h\t%h\n", rm, a, b, o);
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adr <= adr + 1;
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adr <= adr + 1;
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end
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end
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end
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end
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//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
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//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
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DFPMultiplynr u6 (clk, 1'b1, ld, a, b, o, rm, done);//, sign_exe, inf, overflow, underflow);
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DFPMultiplynr u6 (clk, 1'b1, ld, a, b, o, rm, done);//, sign_exe, inf, overflow, underflow);
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endmodule
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endmodule
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