// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// mult32x32_tb.sv
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// mult32x32_tb.sv
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//
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//
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// BSD 3-Clause License
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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// list of conditions and the following disclaimer.
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//
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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module mult32x32_tb();
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module mult32x32_tb();
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reg clk;
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reg clk;
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reg [23:0] count;
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reg [23:0] count;
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reg [31:0] adr;
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reg [31:0] adr;
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reg rst;
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reg rst;
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reg [31:0] a, b;
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reg [31:0] a, b;
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wire [63:0] o;
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wire [63:0] o;
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wire [63:0] p = a * b;
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wire [63:0] p = a * b;
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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mult32x32 u1 (clk, 1'b1, a, b, o);
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mult32x32 u1 (clk, 1'b1, a, b, o);
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integer outfile;
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integer outfile;
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initial begin
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initial begin
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rst = 1'b0;
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rst = 1'b0;
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clk = 1'b0;
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clk = 1'b0;
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#20 rst = 1;
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#20 rst = 1;
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#50 rst = 0;
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#50 rst = 0;
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#1000000 $fclose(outfile);
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#10000000 $fclose(outfile);
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#10 $finish;
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#10 $finish;
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end
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end
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always #5
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always #5
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clk = ~clk;
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clk = ~clk;
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//a25e46ad a76da76d 6a320c6f94e7f2a9 6a310c6f94e7f2a9*
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//147c147c 67589e7f 08460393acd2b184 08450393acd2b184*
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (rst) begin
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if (rst) begin
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adr <= 0;
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adr <= 0;
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count <= 0;
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count <= 0;
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a <= $urandom(1);
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a <= $urandom(1);
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end
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end
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else
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else
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begin
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begin
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if (adr==0) begin
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if (adr==0) begin
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outfile = $fopen("d:/cores2022/rf6809/rtl/fpu/test_bench/mult32x32_tvo.txt", "wb");
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outfile = $fopen("d:/cores2022/rf6809/rtl/fpu/test_bench/mult32x32_tvo.txt", "wb");
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$fwrite(outfile, "--- A --- ---- B ---- - DUT Product - - SIM Product -\n");
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$fwrite(outfile, "--- A --- ---- B ---- - DUT Product - - SIM Product -\n");
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end
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end
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count <= count + 1;
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count <= count + 1;
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if (count > 12)
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if (count > 12)
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count <= 1'd1;
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count <= 1'd1;
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if (count==2) begin
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if (count==2) begin
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case (adr)
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case (adr)
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1:
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1:
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begin
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begin
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a <= 32'd10;
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a <= 32'ha25e46ad;
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b <= 32'd10;
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b <= 32'ha76da76d;
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end
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end
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2:
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2:
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begin
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begin
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a <= 32'd21;
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a <= 32'h147c147c;
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b <= 32'd1700000;
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b <= 32'h67589e7f;
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end
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end
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3:
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3:
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begin
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begin
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a <= 32'd215000;
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a <= 32'd215000;
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b <= 32'd11;
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b <= 32'd11;
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end
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end
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default:
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default:
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begin
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begin
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a[31:0] <= $urandom();
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a[31:0] <= $urandom();
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b[31:0] <= $urandom();
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b[31:0] <= $urandom();
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end
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end
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endcase
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endcase
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end
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end
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if (count==12) begin
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if (count==12) begin
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$fwrite(outfile, "%h\t%h\t%h\t%h%c\n", a, b, o, p,p!=o ? "*":" ");
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$fwrite(outfile, "%h\t%h\t%h\t%h%c\n", a, b, o, p,p!=o ? "*":" ");
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adr <= adr + 1;
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adr <= adr + 1;
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end
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end
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end
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end
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endmodule
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endmodule
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