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Altera
|
Altera
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ip.hwp.cpu
|
ip.hwp.cpu
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nios_ii_sram
|
nios_ii_sram
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1.0
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1.0
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Nios2 SRAM subsystem
|
Nios2 subsystem using SRAM as a data and program memory.
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Includes HIBI_PE_DMA for hibi communication.
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clk
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clk
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false
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false
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CLK
|
CLK
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0
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0
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0
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0
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clk_0
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clk_0
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0
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0
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0
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0
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8
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8
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little
|
little
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hibi_master
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hibi_master
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false
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false
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AV
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AV
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0
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0
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0
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0
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hibi_av_out_from_the_hibi_pe_dma_0
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hibi_av_out_from_the_hibi_pe_dma_0
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0
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0
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0
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0
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COMM
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COMM
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4
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4
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0
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0
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hibi_comm_out_from_the_hibi_pe_dma_0
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hibi_comm_out_from_the_hibi_pe_dma_0
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4
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4
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0
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0
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DATA
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DATA
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31
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31
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0
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0
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hibi_data_out_from_the_hibi_pe_dma_0
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hibi_data_out_from_the_hibi_pe_dma_0
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31
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31
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0
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0
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RE
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RE
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0
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0
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0
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0
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hibi_re_out_from_the_hibi_pe_dma_0
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hibi_re_out_from_the_hibi_pe_dma_0
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0
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0
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0
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0
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WE
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WE
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0
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0
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0
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0
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hibi_we_out_from_the_hibi_pe_dma_0
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hibi_we_out_from_the_hibi_pe_dma_0
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0
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0
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0
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0
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8
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8
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little
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little
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rst_n
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rst_n
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false
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false
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RESETn
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RESETn
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0
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0
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0
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0
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reset_n
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reset_n
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0
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0
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0
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0
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8
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8
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little
|
little
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sram_if
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sram_if
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false
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false
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SRAM_UB_N_FROM_SRAM
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SRAM_UB_N_FROM_SRAM
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0
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0
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0
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0
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SRAM_UB_N_from_the_sram_0
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SRAM_UB_N_from_the_sram_0
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0
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0
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0
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0
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SRAM_WE_N_FROM_SRAM
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SRAM_WE_N_FROM_SRAM
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0
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0
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0
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0
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SRAM_WE_N_from_the_sram_0
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SRAM_WE_N_from_the_sram_0
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0
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0
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0
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0
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SRAM_LB_N_FROM_SRAM
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SRAM_LB_N_FROM_SRAM
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0
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0
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0
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0
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SRAM_LB_N_from_the_sram_0
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SRAM_LB_N_from_the_sram_0
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0
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0
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0
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0
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SRAM_CE_N_FROM_SRAM
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SRAM_CE_N_FROM_SRAM
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0
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0
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0
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0
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SRAM_CE_N_from_the_sram_0
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SRAM_CE_N_from_the_sram_0
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0
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0
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0
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0
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SRAM_OE_N_FROM_SRAM
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SRAM_OE_N_FROM_SRAM
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0
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0
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0
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0
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SRAM_OE_N_from_the_sram_0
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SRAM_OE_N_from_the_sram_0
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0
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0
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0
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0
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SRAM_DQ_TO_AND_FROM_SRAM
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SRAM_DQ_TO_AND_FROM_SRAM
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15
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15
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0
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0
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SRAM_DQ_to_and_from_the_sram_0
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SRAM_DQ_to_and_from_the_sram_0
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15
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15
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0
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0
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SRAM_ADDR_FROM_SRAM
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SRAM_ADDR_FROM_SRAM
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17
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17
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0
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0
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SRAM_ADDR_from_the_sram_0
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SRAM_ADDR_from_the_sram_0
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17
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17
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0
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0
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8
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8
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little
|
little
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hibi_slave
|
hibi_slave
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false
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false
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AV
|
AV
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0
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0
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0
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0
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hibi_av_in_to_the_hibi_pe_dma_0
|
hibi_av_in_to_the_hibi_pe_dma_0
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0
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0
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0
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0
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COMM
|
COMM
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4
|
4
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0
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0
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hibi_comm_in_to_the_hibi_pe_dma_0
|
hibi_comm_in_to_the_hibi_pe_dma_0
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4
|
4
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0
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0
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DATA
|
DATA
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31
|
31
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0
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0
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hibi_data_in_to_the_hibi_pe_dma_0
|
hibi_data_in_to_the_hibi_pe_dma_0
|
|
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31
|
31
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0
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0
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|
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EMPTY
|
EMPTY
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0
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0
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0
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0
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hibi_empty_in_to_the_hibi_pe_dma_0
|
hibi_empty_in_to_the_hibi_pe_dma_0
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0
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0
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0
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0
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FULL
|
FULL
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0
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0
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0
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0
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hibi_full_in_to_the_hibi_pe_dma_0
|
hibi_full_in_to_the_hibi_pe_dma_0
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0
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0
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0
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0
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8
|
8
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little
|
little
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avalon_addr_space
|
avalon_addr_space
|
Avalon address space. (local)
|
Avalon address space. (local)
|
4G
|
4G
|
32
|
32
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.bss
|
.bss
|
0x00800000
|
0x00800000
|
512
|
512
|
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.entry
|
.entry
|
0x00800400
|
0x00800400
|
512
|
512
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.exceptions
|
.exceptions
|
0x00800200
|
0x00800200
|
512
|
512
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.heap
|
.heap
|
0x00800800
|
0x00800800
|
512
|
512
|
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.rodata
|
.rodata
|
0x00800E00
|
0x00800E00
|
512
|
512
|
|
|
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.rwdata
|
.rwdata
|
0x00800A00
|
0x00800A00
|
512
|
512
|
|
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.stack
|
.stack
|
0x00800600
|
0x00800600
|
512
|
512
|
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.text
|
.text
|
0x00800C00
|
0x00800C00
|
512
|
512
|
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|
Shared_memory
|
Shared_memory
|
0x1000000
|
0x1000000
|
4K
|
4K
|
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|
8
|
32
|
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|
avalon_addr_space
|
avalon_addr_space
|
|
|
HIBI_PE_DMA
|
HIBI_PE_DMA
|
0x0
|
0x500
|
4
|
64
|
32
|
32
|
reserved
|
register
|
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|
RX_INITIALIZE
|
|
Initializes the channel
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0
|
|
0x0
|
|
32
|
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false
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write-only
|
|
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|
CONTROL
|
|
Control register
|
|
0
|
|
0x1
|
|
32
|
|
read-write
|
|
|
|
|
|
IRQ_STATUS
|
|
Read IRQ status and acknoledge interrupts
|
|
0
|
|
0x2
|
|
32
|
|
read-write
|
|
|
|
|
|
TX_MEM_ADDR
|
|
Address where data to be sent begins
|
|
0
|
|
0x3
|
|
32
|
|
write-only
|
|
|
|
|
|
TX_WORDS
|
|
How many words to send
|
|
0
|
|
0x4
|
|
32
|
|
read-only
|
|
|
|
|
|
TX_COMM
|
|
Hibi command to send the data with
|
|
0
|
|
0x5
|
|
32
|
|
write-only
|
|
|
|
|
|
TX_HIBI_ADDR
|
|
Hibi address to send the data
|
|
0
|
|
0x6
|
|
32
|
|
write-only
|
|
|
|
|
|
RX_HIBI_DATA
|
|
Current data on hibi rx interface
|
|
0
|
|
0x7
|
|
32
|
|
read-only
|
|
|
|
|
|
RX_MEM_ADDR
|
|
Address where channel n stores received data
|
|
0
|
|
0x8
|
|
32
|
|
read-write
|
|
|
|
|
|
RX_WORDS
|
|
How many words to receive for packet channel n or read
|
|
acknowledge for stream channel n
|
|
0
|
|
0x9
|
|
32
|
|
read-write
|
|
|
|
|
|
RX_HIBI_ADDR
|
|
Hibi address for channel n to listen
|
|
0
|
|
0xA
|
|
32
|
|
read-write
|
|
|
|
|
|
|
JTAG_UART
|
JTAG_UART
|
0x4
|
0x100
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
|
TIMER
|
TIMER
|
0x8
|
0x300
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
|
SRAM
|
SRAM
|
0x00800000
|
0x00800000
|
8M
|
8M
|
32
|
32
|
memory
|
memory
|
|
|
|
|
SYSID
|
SYSID
|
0x10
|
0x200
|
4
|
4
|
32
|
32
|
reserved
|
reserved
|
|
|
|
|
ONCHIP_MEM
|
ONCHIP_MEM
|
0x1000000
|
0x1000000
|
4K
|
4K
|
32
|
32
|
memory
|
memory
|
|
|
|
|
|
|
|
|
hibi_addr_space
|
hibi_addr_space
|
HIBI address space
|
HIBI address space
|
4G
|
4G
|
32
|
32
|
8
|
8
|
|
|
|
|
|
|
|
|
hibi_mem_map
|
hibi_mem_map
|
|
|
|
hibi_addr_block
|
|
0x0
|
|
32
|
|
32
|
|
reserved
|
|
|
32
|
32
|
|
|
|
|
|
|
|
|
|
|
rtl
|
rtl
|
VHDL:Quartus:
|
VHDL:Quartus:
|
nios_ii_sram
|
nios_ii_sram
|
|
|
hdlSources
|
hdlSources
|
|
|
|
|
|
|
|
|
|
|
SRAM_ADDR_from_the_sram_0
|
SRAM_ADDR_from_the_sram_0
|
|
|
out
|
out
|
|
|
17
|
17
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
SRAM_CE_N_from_the_sram_0
|
SRAM_CE_N_from_the_sram_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
SRAM_DQ_to_and_from_the_sram_0
|
SRAM_DQ_to_and_from_the_sram_0
|
|
|
inout
|
inout
|
|
|
15
|
15
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
SRAM_LB_N_from_the_sram_0
|
SRAM_LB_N_from_the_sram_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
SRAM_OE_N_from_the_sram_0
|
SRAM_OE_N_from_the_sram_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
SRAM_UB_N_from_the_sram_0
|
SRAM_UB_N_from_the_sram_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
SRAM_WE_N_from_the_sram_0
|
SRAM_WE_N_from_the_sram_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
clk_0
|
clk_0
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_av_in_to_the_hibi_pe_dma_0
|
hibi_av_in_to_the_hibi_pe_dma_0
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_av_out_from_the_hibi_pe_dma_0
|
hibi_av_out_from_the_hibi_pe_dma_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
hibi_comm_in_to_the_hibi_pe_dma_0
|
hibi_comm_in_to_the_hibi_pe_dma_0
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_comm_out_from_the_hibi_pe_dma_0
|
hibi_comm_out_from_the_hibi_pe_dma_0
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_data_in_to_the_hibi_pe_dma_0
|
hibi_data_in_to_the_hibi_pe_dma_0
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_data_out_from_the_hibi_pe_dma_0
|
hibi_data_out_from_the_hibi_pe_dma_0
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
hibi_empty_in_to_the_hibi_pe_dma_0
|
hibi_empty_in_to_the_hibi_pe_dma_0
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
hibi_full_in_to_the_hibi_pe_dma_0
|
hibi_full_in_to_the_hibi_pe_dma_0
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
hibi_re_out_from_the_hibi_pe_dma_0
|
hibi_re_out_from_the_hibi_pe_dma_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
hibi_we_out_from_the_hibi_pe_dma_0
|
hibi_we_out_from_the_hibi_pe_dma_0
|
|
|
out
|
out
|
|
|
|
|
|
|
|
|
reset_n
|
reset_n
|
|
|
in
|
in
|
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hdlSources
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hdlSources
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hdl/timer_0.v
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hdl/timer_0.v
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verilogSource
|
verilogSource
|
false
|
false
|
|
|
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hdl/cpu_0.v
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hdl/cpu_0.v
|
verilogSource
|
verilogSource
|
false
|
false
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|
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hdl/cpu_0_jtag_debug_module_sysclk.v
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hdl/cpu_0_jtag_debug_module_sysclk.v
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verilogSource
|
verilogSource
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false
|
false
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|
|
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hdl/cpu_0_jtag_debug_module_tck.v
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hdl/cpu_0_jtag_debug_module_tck.v
|
verilogSource
|
verilogSource
|
false
|
false
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|
|
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|
hdl/cpu_0_jtag_debug_module_wrapper.v
|
hdl/cpu_0_jtag_debug_module_wrapper.v
|
verilogSource
|
verilogSource
|
false
|
false
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|
|
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hdl/cpu_0_mult_cell.v
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hdl/cpu_0_mult_cell.v
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verilogSource
|
verilogSource
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false
|
false
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|
|
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hdl/cpu_0_oci_test_bench.v
|
hdl/cpu_0_oci_test_bench.v
|
verilogSource
|
verilogSource
|
false
|
false
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|
|
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hdl/cpu_0_test_bench.v
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hdl/cpu_0_test_bench.v
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verilogSource
|
verilogSource
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false
|
false
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hdl/jtag_uart_0.v
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hdl/jtag_uart_0.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
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|
hdl/nios_ii_sram.v
|
hdl/nios_ii_sram.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
|
hdl/sram_0.v
|
hdl/sram_0.v
|
verilogSource
|
verilogSource
|
false
|
false
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hdl/nios_ii_sram.qip
|
hdl/nios_ii_sram.qip
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quartusIPFile
|
quartusIPFile
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false
|
false
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hdl/sysid.v
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hdl/sysid.v
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verilogSource
|
verilogSource
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false
|
false
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hdl/ip/hpd_rx_stream.vhd
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hdl/ip/hpd_rx_stream.vhd
|
vhdlSource
|
vhdlSource
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false
|
false
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|
|
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hdl/ip/hpd_tx_control.vhd
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hdl/ip/hpd_tx_control.vhd
|
vhdlSource
|
vhdlSource
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false
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false
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|
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hdl/ip/hibi_pe_dma.vhd
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hdl/ip/hibi_pe_dma.vhd
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vhdlSource
|
vhdlSource
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false
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false
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hdl/ip/hibi_pe_dma_hw.tcl
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hdl/ip/hibi_pe_dma_hw.tcl
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tclScript
|
tclScript
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false
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false
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hdl/ip/hibi_pe_dma_sw.tcl
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hdl/ip/hibi_pe_dma_sw.tcl
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tclScript
|
tclScript
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false
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false
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hdl/ip/hpd_rx_and_conf.vhd
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hdl/ip/hpd_rx_and_conf.vhd
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vhdlSource
|
vhdlSource
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false
|
false
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|
|
|
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hdl/ip/hpd_rx_packet.vhd
|
hdl/ip/hpd_rx_packet.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
hdl/onchip_memory_0.v
|
hdl/onchip_memory_0.v
|
verilogSource
|
verilogSource
|
false
|
false
|
|
|
|
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avalon_addr_space_header
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Contains header files generated for the component.
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generatedFiles
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headers/avalon_addr_space.h
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cSource
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cppSource
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true
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A header file generated by Kactus2.
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This file contains the register and memory addresses defined in the memory map(s)
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nios2
|
nios2
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IP
|
IP
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HW
|
HW
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Fixed
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Fixed
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software
|
software
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