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TUT
|
TUT
|
ip.hwp.communication
|
ip.hwp.communication
|
hibi_wrapper_r3
|
hibi_wrapper_r3
|
3.0
|
3.0
|
HIBI bus wrapper, interface revision 3
|
HIBI bus wrapper, interface revision 3
|
|
|
|
|
|
|
bus_mMaster
|
bus_mMaster
|
HIBI bus Master interface
|
HIBI bus Master interface
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AV
|
AV
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_av_in
|
bus_av_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
bus_comm_in
|
bus_comm_in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
LOCK
|
LOCK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_Lock_in
|
bus_Lock_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
FULL
|
FULL
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_full_in
|
bus_full_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
bus_data_in
|
bus_data_in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
bus_mSlave
|
bus_mSlave
|
HIBI bus Slave interface
|
HIBI bus Slave interface
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AV
|
AV
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_av_out
|
bus_av_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
bus_comm_out
|
bus_comm_out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
LOCK
|
LOCK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_Lock_out
|
bus_Lock_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
FULL
|
FULL
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_full_out
|
bus_full_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
bus_data_out
|
bus_data_out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
ip_mMaster
|
ip_mMaster
|
HIBI IP master interface
|
HIBI IP master interface
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
ADDR
|
ADDR
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_addr_in
|
agent_addr_in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_data_in
|
agent_data_in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
agent_comm_in
|
agent_comm_in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
RE
|
RE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_re_in
|
agent_re_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
WE
|
WE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_we_in
|
agent_we_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_WE
|
MSG_WE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_msg_we_in
|
agent_msg_we_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_ADDR
|
MSG_ADDR
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_msg_addr_in
|
agent_msg_addr_in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_COMM
|
MSG_COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
agent_msg_comm_in
|
agent_msg_comm_in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_DATA
|
MSG_DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_msg_data_in
|
agent_msg_data_in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_RE
|
MSG_RE
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_msg_re_in
|
agent_msg_re_in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
ip_mSlave
|
ip_mSlave
|
HIBI IP slave interface
|
HIBI IP slave interface
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
ADDR
|
ADDR
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_addr_out
|
agent_addr_out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
COMM
|
COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
agent_comm_out
|
agent_comm_out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
DATA
|
DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_data_out
|
agent_data_out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
EMPTY
|
EMPTY
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_empty_out
|
agent_empty_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
FULL
|
FULL
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_full_out
|
agent_full_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_ADDR
|
MSG_ADDR
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_msg_addr_out
|
agent_msg_addr_out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_COMM
|
MSG_COMM
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
agent_msg_comm_out
|
agent_msg_comm_out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_DATA
|
MSG_DATA
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
agent_msg_data_out
|
agent_msg_data_out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_EMPTY
|
MSG_EMPTY
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_msg_empty_out
|
agent_msg_empty_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_FULL
|
MSG_FULL
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_msg_full_out
|
agent_msg_full_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_ONE_P
|
MSG_ONE_P
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_msg_one_p_out
|
agent_msg_one_p_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
ONE_P
|
ONE_P
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_one_p_out
|
agent_one_p_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
ONE_D
|
ONE_D
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_one_d_out
|
agent_one_d_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
MSG_ONE_D
|
MSG_ONE_D
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_msg_one_d_out
|
agent_msg_one_d_out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
clocks
|
clocks
|
HIBI clock inputs
|
HIBI clock inputs
|
|
|
|
|
|
|
false
|
false
|
|
|
|
|
|
|
AGENT_CLK
|
AGENT_CLK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_clk
|
agent_clk
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
AGENT_SYNC_CLK
|
AGENT_SYNC_CLK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
agent_sync_clk
|
agent_sync_clk
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
BUS_CLK
|
BUS_CLK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_clk
|
bus_clk
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
BUS_SYNC_CLK
|
BUS_SYNC_CLK
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
bus_sync_clk
|
bus_sync_clk
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
8
|
8
|
little
|
little
|
|
|
|
|
|
|
|
|
hibi_ip_master_channel
|
hibi_ip_master_channel
|
ip_mMaster
|
ip_mMaster
|
bus_mSlave
|
bus_mSlave
|
|
|
|
|
hibi_ip_slave_channel
|
hibi_ip_slave_channel
|
ip_mSlave
|
ip_mSlave
|
bus_mMaster
|
bus_mMaster
|
|
|
|
|
|
|
|
|
|
|
rtl
|
rtl
|
VHDL::
|
VHDL::
|
|
|
hdlSources
|
hdlSources
|
|
|
|
|
fifo_rtl
|
fifo_rtl
|
|
|
|
|
|
|
|
|
|
|
agent_addr_in
|
agent_addr_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
agent_addr_out
|
agent_addr_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_clk
|
agent_clk
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_comm_in
|
agent_comm_in
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
agent_comm_out
|
agent_comm_out
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_data_in
|
agent_data_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
agent_data_out
|
agent_data_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_empty_out
|
agent_empty_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_full_out
|
agent_full_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_addr_in
|
agent_msg_addr_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
agent_msg_addr_out
|
agent_msg_addr_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_comm_in
|
agent_msg_comm_in
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
agent_msg_comm_out
|
agent_msg_comm_out
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_data_in
|
agent_msg_data_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
(others => '0')
|
(others => '0')
|
|
|
|
|
|
|
|
|
|
|
agent_msg_data_out
|
agent_msg_data_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_empty_out
|
agent_msg_empty_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_full_out
|
agent_msg_full_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_one_p_out
|
agent_msg_one_p_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_re_in
|
agent_msg_re_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
agent_msg_we_in
|
agent_msg_we_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
agent_one_p_out
|
agent_one_p_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_re_in
|
agent_re_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
agent_sync_clk
|
agent_sync_clk
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
agent_we_in
|
agent_we_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
'0'
|
'0'
|
|
|
|
|
|
|
|
|
|
|
bus_Lock_in
|
bus_Lock_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_Lock_out
|
bus_Lock_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_av_in
|
bus_av_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_av_out
|
bus_av_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_clk
|
bus_clk
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_comm_in
|
bus_comm_in
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_comm_out
|
bus_comm_out
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_data_in
|
bus_data_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_data_out
|
bus_data_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_full_in
|
bus_full_in
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
bus_full_out
|
bus_full_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
bus_sync_clk
|
bus_sync_clk
|
|
|
in
|
in
|
|
|
|
|
|
|
|
|
rst_n
|
rst_n
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_one_d_out
|
agent_one_d_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
agent_msg_one_d_out
|
agent_msg_one_d_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr_g
|
addr_g
|
addressing settings: unique for each wrapper
|
addressing settings: unique for each wrapper
|
46
|
46
|
|
|
|
|
addr_limit_g
|
addr_limit_g
|
Upper address boundary
|
Upper address boundary
|
0
|
0
|
|
|
|
|
addr_width_g
|
addr_width_g
|
HIBI address width
|
HIBI address width
|
32
|
32
|
|
|
|
|
arb_type
|
arb_type
|
Arbitration type 0 round-robin, 1 priority, 2 combined, 3 DAA. Ensure that all wrappers in a segment agree on arb_type
|
Arbitration type 0 round-robin, 1 priority, 2 combined, 3 DAA. Ensure that all wrappers in a segment agree on arb_type
|
0
|
0
|
|
|
|
|
cfg_re_g
|
cfg_re_g
|
enable reading config
|
enable reading config
|
0
|
0
|
|
|
|
|
cfg_we_g
|
cfg_we_g
|
enable writing config
|
enable writing config
|
0
|
0
|
|
|
|
|
comm_width_g
|
comm_width_g
|
HIBI communication width (HIBI v.2=3, v.3 = 5 bits)
|
HIBI communication width (HIBI v.2=3, v.3 = 5 bits)
|
5
|
5
|
|
|
|
|
counter_width_g
|
counter_width_g
|
greater than or equal (n_agents, max_send...)
|
greater than or equal (n_agents, max_send...)
|
7
|
7
|
|
|
|
|
data_width_g
|
data_width_g
|
HIBI data width (less than or equal)
|
HIBI data width (less than or equal)
|
32
|
32
|
|
|
|
|
debug_width_g
|
debug_width_g
|
For special monitors
|
For special monitors
|
0
|
0
|
|
|
|
|
fifo_sel_g
|
fifo_sel_g
|
fifo_sel: 0 synch multiclk, 1 basic GALS, 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)
|
fifo_sel: 0 synch multiclk, 1 basic GALS, 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)
|
0
|
0
|
|
|
|
|
id_g
|
id_g
|
used instead of addr in recfg
|
used instead of addr in recfg
|
5
|
5
|
|
|
|
|
id_max_g
|
id_max_g
|
Only for bridges+cfg, zero for others!
|
Only for bridges+cfg, zero for others!
|
0
|
0
|
|
|
|
|
id_min_g
|
id_min_g
|
Only for bridges+cfg, zero for others!
|
Only for bridges+cfg, zero for others!
|
0
|
0
|
|
|
|
|
id_width_g
|
id_width_g
|
gte(log2(id_g))
|
gte(log2(id_g))
|
4
|
4
|
|
|
|
|
inv_addr_en_g
|
inv_addr_en_g
|
Only for bridges
|
Only for bridges
|
0
|
0
|
|
|
|
|
keep_slot_g
|
keep_slot_g
|
for TDMA
|
for TDMA
|
0
|
0
|
|
|
|
|
max_send
|
max_send
|
in words. Max_send can be wrapper-specific.
|
in words. Max_send can be wrapper-specific.
|
50
|
50
|
|
|
|
|
n_agents
|
n_agents
|
Number of agents within one segment. Ensure that all wrappers in a segment agree on n_agents
|
Number of agents within one segment. Ensure that all wrappers in a segment agree on n_agents
|
4
|
4
|
|
|
|
|
n_cfg_pages_g
|
n_cfg_pages_g
|
Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages
|
Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages
|
0
|
0
|
|
|
|
|
n_extra_params_g
|
n_extra_params_g
|
app-specific registers
|
app-specific registers
|
0
|
0
|
|
|
|
|
n_time_slots_g
|
n_time_slots_g
|
TDMA is enabled by setting n_time_slots > 0
|
TDMA is enabled by setting n_time_slots > 0
|
0
|
0
|
|
|
|
|
prior_g
|
prior_g
|
lte n_agents
|
lte n_agents
|
2
|
2
|
|
|
|
|
rel_agent_freq_g
|
rel_agent_freq_g
|
Synch_multiclk FIFOs must know the ratio of frequencies
|
Synch_multiclk FIFOs must know the ratio of frequencies
|
1
|
1
|
|
|
|
|
rel_bus_freq_g
|
rel_bus_freq_g
|
Synch_multiclk FIFOs must know the ratio of frequencies
|
Synch_multiclk FIFOs must know the ratio of frequencies
|
1
|
1
|
|
|
|
|
rx_fifo_depth_g
|
rx_fifo_depth_g
|
All FIFO depths are given in words. Allowed values 0,2,3... words.
|
All FIFO depths are given in words. Allowed values 0,2,3... words.
|
5
|
5
|
|
|
|
|
rx_msg_fifo_depth_g
|
rx_msg_fifo_depth_g
|
All FIFO depths are given in words. Allowed values 0,2,3... words.Prefix msg refers to hi-prior data
|
All FIFO depths are given in words. Allowed values 0,2,3... words.Prefix msg refers to hi-prior data
|
5
|
5
|
|
|
|
|
separate_addr_g
|
separate_addr_g
|
Transmits addr in parallel with data
|
Transmits addr in parallel with data
|
0
|
0
|
|
|
|
|
tx_fifo_depth_g
|
tx_fifo_depth_g
|
All FIFO depths are given in words. Allowed values 0,2,3... words.
|
All FIFO depths are given in words. Allowed values 0,2,3... words.
|
5
|
5
|
|
|
|
|
tx_msg_fifo_depth_g
|
tx_msg_fifo_depth_g
|
All FIFO depths are given in words. Allowed values 0,2,3... words.Prefix msg refers to hi-prior data
|
All FIFO depths are given in words. Allowed values 0,2,3... words.Prefix msg refers to hi-prior data
|
5
|
5
|
|
|
|
|
|
|
|
|
|
|
hdlSources
|
hdlSources
|
VHDL for HIBI wrapper, its subcomonents and the segment that connects several wrappers together. Note that FIFOs are in different directory so that other NoCs can use them also.
|
VHDL for HIBI wrapper, its subcomonents and the segment that connects several wrappers together. Note that FIFOs are in different directory so that other NoCs can use them also.
|
|
|
../vhd/tx_control.vhd
|
../vhd/tx_control.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/addr_data_demux_read.vhd
|
../vhd/addr_data_demux_read.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/addr_data_mux_write.vhd
|
../vhd/addr_data_mux_write.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/addr_decoder.vhd
|
../vhd/addr_decoder.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/cfg_init_pkg.vhd
|
../vhd/cfg_init_pkg.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/cfg_mem.vhd
|
../vhd/cfg_mem.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/double_fifo_demux_wr.vhd
|
../vhd/double_fifo_demux_wr.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/double_fifo_mux_rd.vhd
|
../vhd/double_fifo_mux_rd.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/dyn_arb.vhd
|
../vhd/dyn_arb.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/fifo_demux_wr.vhd
|
../vhd/fifo_demux_wr.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/fifo_mux_rd.vhd
|
../vhd/fifo_mux_rd.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/hibi_wrapper_r1.vhd
|
../vhd/hibi_wrapper_r1.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/hibi_wrapper_r3.vhd
|
../vhd/hibi_wrapper_r3.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/hibiv3_pkg.vhd
|
../vhd/hibiv3_pkg.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/lfsr.vhd
|
../vhd/lfsr.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/receiver.vhd
|
../vhd/receiver.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/rx_control.vhd
|
../vhd/rx_control.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../vhd/transmitter.vhd
|
../vhd/transmitter.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
vhdlSource
|
vhdlSource
|
Default file builders
|
Default file builders
|
vcom
|
vcom
|
-work hibi -check_synthesis -quiet
|
-work hibi -check_synthesis -quiet
|
false
|
false
|
|
|
../../../../ip.hwp.storage/fifos
|
../../../../ip.hwp.storage/fifos
|
|
|
|
|
fifo_rtl
|
fifo_rtl
|
Various FIFO buffers and synchronizers.
|
Various FIFO buffers and synchronizers.
|
sourceFiles
|
sourceFiles
|
|
|
../../../../ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
|
../../../../ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
|
../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
|
../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
|
vhdlSource
|
vhdlSource
|
false
|
false
|
|
|
|
|
vhdlSource
|
vhdlSource
|
vcom
|
vcom
|
-work hibi -check_synthesis -quiet
|
-work hibi -check_synthesis -quiet
|
false
|
false
|
|
|
Double click to add new item.
|
|
|
|
|
|
doc
|
doc
|
Documentation for HIBI v3.0.
|
Documentation for HIBI v3.0.
|
|
|
../doc/clock_distribution_readme.txt
|
../doc/clock_distribution_readme.txt
|
ASCII
|
ASCII
|
false
|
false
|
|
|
|
|
../doc/hibi_v2_to_v3.pptx
|
../doc/hibi_v2_to_v3.pptx
|
powerPoint
|
powerPoint
|
false
|
false
|
|
|
|
|
../doc/hibi_v3_datasheet_2011_11_15.pdf
|
../doc/hibi_v3_datasheet_2011_11_15.pdf
|
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