-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Address translation unit
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-- Title : Address translation unit
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : addr_translation.vhd
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-- File : addr_translation.vhd
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-- Author : Lasse Lehtonen
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-- Author : Lasse Lehtonen
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-- Company :
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-- Company :
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-- Created : 2011-10-12
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-- Created : 2011-10-12
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-- Last update: 2012-03-19
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-- Last update: 2012-05-04
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-- Platform :
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-- Platform :
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-- Standard : VHDL'87
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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--
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--
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-- Translates various addressing styles to network adresses and also
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-- Translates various addressing styles to network adresses and also
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-- handles inserting the original address behind the network address flit.
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-- handles inserting the original address behind the network address flit.
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--
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--
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-- Generics:
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-- Generics:
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--
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--
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-- address_mode_g 0 : IP gives raw network address
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-- address_mode_g 0 : IP gives raw network address
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-- address_mode_g 1 : IP gives integer ID numbers as target address
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-- address_mode_g 1 : IP gives integer ID numbers as target address
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-- address_mode_g 2 : IP gives memory mapped addresses
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-- address_mode_g 2 : IP gives memory mapped addresses
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--
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--
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-- addr_flit_en_g 0 : Nothing done
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-- addr_flit_en_g 0 : Nothing done
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-- addr_flit_en_g 1 : Places the original address to the second flit
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-- addr_flit_en_g 1 : Places the original address to the second flit
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2011
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-- Copyright (c) 2011
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Date Version Author Description
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-- Date Version Author Description
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-- 2011-10-12 1.0 lehton87 Created
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-- 2011-10-12 1.0 lehton87 Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity addr_translation is
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entity addr_translation is
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generic (
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generic (
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my_id_g : natural;
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my_id_g : natural;
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cmd_width_g : positive;
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cmd_width_g : positive;
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data_width_g : positive;
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data_width_g : positive;
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address_mode_g : natural;
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address_mode_g : natural;
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cols_g : positive;
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cols_g : positive;
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rows_g : positive;
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rows_g : positive;
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agents_g : positive;
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agents_g : positive;
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agent_ports_g : positive;
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agent_ports_g : positive;
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addr_flit_en_g : natural;
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addr_flit_en_g : natural;
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noc_type_g : natural
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noc_type_g : natural;
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len_width_g : natural -- 2012-05-04
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);
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);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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-- from IP side
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-- from IP side
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ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
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ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
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ip_data_in : in std_logic_vector(data_width_g-1 downto 0);
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ip_data_in : in std_logic_vector(data_width_g-1 downto 0);
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ip_stall_out : out std_logic;
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ip_stall_out : out std_logic;
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ip_len_in : in std_logic_vector(len_width_g-1 downto 0); -- 2012-05-04
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-- to NET
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-- to NET
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net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
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net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
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net_data_out : out std_logic_vector(data_width_g-1 downto 0);
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net_data_out : out std_logic_vector(data_width_g-1 downto 0);
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net_stall_in : in std_logic;
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net_stall_in : in std_logic;
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orig_addr_out : out std_logic_vector(data_width_g-1 downto 0));
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orig_addr_out : out std_logic_vector(data_width_g-1 downto 0));
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end addr_translation;
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end addr_translation;
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architecture rtl of addr_translation is
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architecture rtl of addr_translation is
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signal addr_to_lut : std_logic_vector(data_width_g-1 downto 0);
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signal addr_to_lut : std_logic_vector(data_width_g-1 downto 0);
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signal addr_from_lut : std_logic_vector(data_width_g-1 downto 0);
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signal addr_from_lut : std_logic_vector(data_width_g-1 downto 0);
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signal orig_addr_r : std_logic_vector(data_width_g-1 downto 0);
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signal orig_addr_r : std_logic_vector(data_width_g-1 downto 0);
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begin -- rtl
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begin -- rtl
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safe_p: process (ip_cmd_in, ip_data_in)
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safe_p : process (ip_cmd_in, ip_data_in)
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begin -- process safe_p
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begin -- process safe_p
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if ip_cmd_in = "01" then
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if ip_cmd_in = "01" then
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addr_to_lut <= ip_data_in;
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addr_to_lut <= ip_data_in;
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else
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else
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addr_to_lut <= (others => '0');
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addr_to_lut <= (others => '0');
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end if;
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end if;
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end process safe_p;
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end process safe_p;
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addr_lut_1 : entity work.address_lut
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addr_lut_1 : entity work.address_lut
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generic map (
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generic map (
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my_id_g => my_id_g,
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my_id_g => my_id_g,
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data_width_g => data_width_g,
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data_width_g => data_width_g,
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address_mode_g => address_mode_g,
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address_mode_g => address_mode_g,
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cols_g => cols_g,
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cols_g => cols_g,
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rows_g => rows_g,
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rows_g => rows_g,
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agent_ports_g => agent_ports_g,
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agent_ports_g => agent_ports_g,
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agents_g => agents_g,
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agents_g => agents_g,
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noc_type_g => noc_type_g
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noc_type_g => noc_type_g,
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len_width_g => len_width_g -- 2012-05-04
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)
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)
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port map (
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port map (
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addr_in => addr_to_lut,
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addr_in => addr_to_lut,
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len_in => ip_len_in, -- 2012-05-04
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addr_out => addr_from_lut
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addr_out => addr_from_lut
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);
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);
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net_cmd_out <= ip_cmd_in;
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net_cmd_out <= ip_cmd_in;
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ip_stall_out <= net_stall_in;
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ip_stall_out <= net_stall_in;
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orig_addr_out <= orig_addr_r;
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orig_addr_out <= orig_addr_r;
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oa_p : process (clk, rst_n)
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oa_p : process (clk, rst_n)
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begin -- process oa_p
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begin -- process oa_p
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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orig_addr_r <= (others => '0');
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orig_addr_r <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if ip_cmd_in = "01" then
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if ip_cmd_in = "01" then
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orig_addr_r <= ip_data_in;
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orig_addr_r <= ip_data_in;
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end if;
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end if;
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end if;
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end if;
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end process oa_p;
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end process oa_p;
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mux_p : process (ip_cmd_in, addr_from_lut, ip_data_in)
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mux_p : process (ip_cmd_in, addr_from_lut, ip_data_in)
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begin -- process mux_p
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begin -- process mux_p
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if ip_cmd_in = "01" then
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if ip_cmd_in = "01" then
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net_data_out <= addr_from_lut;
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net_data_out <= addr_from_lut;
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else
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else
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net_data_out <= ip_data_in;
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net_data_out <= ip_data_in;
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end if;
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end if;
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end process mux_p;
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end process mux_p;
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end rtl;
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end rtl;
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