URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
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| Rev 161 |
Rev 165 |
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TUT
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TUT
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ip.hwp.interface
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ip.hwp.interface
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hibi_udp
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hibi_udp
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1.0
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1.0
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clk_udp
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clk
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false
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false
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CLK
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CLK
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0
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0
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0
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0
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clk_udp
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clk
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0
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0
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0
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0
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8
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8
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little
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little
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hibi_master
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hibi_master
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false
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false
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AV
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AV
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0
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0
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0
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0
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hibi_av_out
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hibi_av_out
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0
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0
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0
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0
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COMM
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COMM
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4
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4
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0
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0
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hibi_comm_out
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hibi_comm_out
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4
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4
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0
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0
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DATA
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DATA
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31
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31
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0
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0
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hibi_data_out
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hibi_data_out
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31
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31
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0
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0
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RE
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RE
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0
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0
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0
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0
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hibi_re_out
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hibi_re_out
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0
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0
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0
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0
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WE
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WE
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0
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0
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0
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0
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hibi_we_out
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hibi_we_out
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0
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0
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0
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0
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8
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8
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little
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little
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hibi_slave
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hibi_slave
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false
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false
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AV
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AV
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0
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0
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0
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0
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hibi_av_in
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hibi_av_in
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0
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0
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0
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0
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COMM
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COMM
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4
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4
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0
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0
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hibi_comm_in
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hibi_comm_in
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4
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4
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0
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0
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DATA
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DATA
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31
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31
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0
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0
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hibi_data_in
|
hibi_data_in
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31
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31
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0
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0
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EMPTY
|
EMPTY
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0
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0
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0
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0
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hibi_empty_in
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hibi_empty_in
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0
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0
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0
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0
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FULL
|
FULL
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0
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0
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0
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0
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hibi_full_in
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hibi_full_in
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0
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0
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0
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0
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8
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8
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little
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little
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clk
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clk_udp
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false
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false
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CLK
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CLK
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0
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0
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0
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0
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clk
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clk_udp
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0
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0
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0
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0
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8
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8
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little
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little
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DM9000A
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DM9000A
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false
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false
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eth_chip_sel_out
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eth_chip_sel_out
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0
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0
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0
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0
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eth_chip_sel_out
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eth_chip_sel_out
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0
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0
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0
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0
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eth_clk_out
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eth_clk_out
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0
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0
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0
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0
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eth_clk_out
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eth_clk_out
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0
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0
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0
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0
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eth_cmd_out
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eth_cmd_out
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0
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0
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0
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0
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eth_cmd_out
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eth_cmd_out
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0
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0
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0
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0
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eth_data_inout
|
eth_data_inout
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15
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15
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0
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0
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eth_data_inout
|
eth_data_inout
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15
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15
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0
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0
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eth_interrupt_in
|
eth_interrupt_in
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0
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0
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0
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0
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eth_interrupt_in
|
eth_interrupt_in
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0
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0
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0
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0
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eth_read_out
|
eth_read_out
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0
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0
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0
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0
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eth_read_out
|
eth_read_out
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0
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0
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0
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0
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eth_reset_out
|
eth_reset_out
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0
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0
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0
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0
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eth_reset_out
|
eth_reset_out
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|
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0
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0
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0
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0
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eth_write_out
|
eth_write_out
|
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0
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0
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0
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0
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eth_write_out
|
eth_write_out
|
|
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0
|
0
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0
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0
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8
|
8
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little
|
little
|
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rst_n
|
rst_n
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false
|
false
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RESETn
|
RESETn
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0
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0
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0
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0
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rst_n
|
rst_n
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0
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0
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0
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0
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8
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8
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little
|
little
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structural
|
structural
|
::
|
::
|
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structural_vhd
|
structural_vhd
|
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structural_vhd
|
structural_vhd
|
VHDL:Kactus2:
|
VHDL:Kactus2:
|
vhdl
|
vhdl
|
hibi_udp
|
hibi_udp
|
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structural_vhdlSource
|
structural_vhdlSource
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clk
|
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in
|
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0
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0
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|
|
|
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|
std_logic
|
|
IEEE.std_logic_1164.all
|
|
rtl
|
|
structural
|
|
structural_vhd
|
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clk_udp
|
clk_udp
|
|
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in
|
in
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|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
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|
hibi_av_out
|
hibi_av_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
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|
|
hibi_comm_out
|
hibi_comm_out
|
|
|
out
|
out
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
std_logic_vector
|
std_logic_vector
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
|
|
|
hibi_data_out
|
hibi_data_out
|
|
|
out
|
out
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
std_logic_vector
|
std_logic_vector
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
|
|
|
hibi_re_out
|
hibi_re_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
|
|
|
hibi_we_out
|
hibi_we_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
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|
hibi_av_in
|
hibi_av_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
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|
hibi_comm_in
|
hibi_comm_in
|
|
|
in
|
in
|
|
|
4
|
4
|
0
|
0
|
|
|
|
|
|
|
std_logic_vector
|
std_logic_vector
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
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|
hibi_data_in
|
hibi_data_in
|
|
|
in
|
in
|
|
|
31
|
31
|
0
|
0
|
|
|
|
|
|
|
std_logic_vector
|
std_logic_vector
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
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|
|
hibi_empty_in
|
hibi_empty_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
|
|
|
hibi_full_in
|
hibi_full_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
std_logic
|
std_logic
|
IEEE.std_logic_1164.all
|
IEEE.std_logic_1164.all
|
rtl
|
rtl
|
structural
|
structural
|
structural_vhd
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
|
|
|
eth_chip_sel_out
|
eth_chip_sel_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_clk_out
|
eth_clk_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_cmd_out
|
eth_cmd_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_data_inout
|
eth_data_inout
|
|
|
inout
|
inout
|
|
|
15
|
15
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_interrupt_in
|
eth_interrupt_in
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_read_out
|
eth_read_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_reset_out
|
eth_reset_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
eth_write_out
|
eth_write_out
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
rst_n
|
rst_n
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
|
|
in
|
|
|
|
0
|
|
0
|
|
|
|
|
|
|
|
std_logic
|
|
IEEE.std_logic_1164.all
|
|
rtl
|
|
structural
|
|
structural_vhd
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
structural_vhdlSource
|
structural_vhdlSource
|
sourceFiles
|
sourceFiles
|
|
|
vhd/hibi_udp.vhd
|
vhd/hibi_udp.vhd
|
vhdlSource
|
vhdlSource
|
true
|
true
|
work
|
work
|
|
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
|
|
vhdlSource
|
vhdlSource
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
vhdlSource-87
|
vhdlSource-87
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
vhdlSource-93
|
vhdlSource-93
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
|
|
|
|
|
|
|
|
IP
|
IP
|
HW
|
HW
|
Parameterizable
|
Parameterizable
|
|
|
|
|
|
|
|
|
|
|
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