-- ***************************************************
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-- ***************************************************
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-- File: basic_tester_hibi_example.vhd
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-- File: basic_tester_hibi_example.vhd
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-- Creation date: 02.07.2012
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-- Creation date: 21.11.2012
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-- Creation time: 15:50:14
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-- Creation time: 14:28:17
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-- Description: Simple example on how to use basic_tester with hibi.
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-- Description: Simple example on how to use basic_tester with hibi.
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-- Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.
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-- Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.
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--
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--
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-- Tx sends few words to rx which takes and checks them.
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-- Tx sends few words to rx which takes and checks them.
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-- Basic_tester is meant for simulation only.
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-- Basic_tester is meant for simulation only.
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-- Created by: matilail
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-- Created by: matilail
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-- This file was generated with Kactus2 vhdl generator.
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-- This file was generated with Kactus2 vhdl generator.
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-- ***************************************************
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-- ***************************************************
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library IEEE;
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library IEEE;
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library work;
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library work;
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use work.all;
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use work.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity basic_tester_hibi_example is
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entity basic_tester_hibi_example is
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end basic_tester_hibi_example;
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end basic_tester_hibi_example;
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-- Instantiates hibi as segement.
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-- Instantiates hibi as segement.
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-- Graphical block diagram view. Hence, its type is "hierarchical".
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-- Graphical block diagram view. Hence, its type is "hierarchical".
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architecture structural_seg of basic_tester_hibi_example is
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architecture structural_seg of basic_tester_hibi_example is
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM : std_logic_vector(4 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM : std_logic_vector(4 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA : std_logic_vector(31 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA : std_logic_vector(31 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D : std_logic;
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signal basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE : std_logic;
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signal basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE : std_logic;
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signal clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK : std_logic;
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signal clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK : std_logic;
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signal rst_r_nRESETn : std_logic;
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signal rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM : std_logic_vector(4 downto 0);
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM : std_logic_vector(4 downto 0);
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA : std_logic_vector(31 downto 0);
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA : std_logic_vector(31 downto 0);
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL : std_logic;
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL : std_logic;
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P : std_logic;
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE : std_logic;
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-- Simple unit for receiving test data. There are separate units for transmitting (tx) and receiving (rx). This one can check the data coming from a IP (e.g. via HIBI). The other unit can send the commands to the tested IP.
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-- Simple unit for receiving test data. There are separate units for transmitting (tx) and receiving (rx). This one can check the data coming from a IP (e.g. via HIBI). The other unit can send the commands to the tested IP.
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--
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--
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-- This IP-XACT component is fixed to 32-bit data and 5-bit command.
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-- This IP-XACT component is fixed to 32-bit data and 5-bit command.
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--
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--
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-- Works only in simulation because configuration is done with ASCII file.
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-- Works only in simulation because configuration is done with ASCII file.
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component basic_tester_rx
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component basic_tester_rx
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generic (
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generic (
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comm_width_g : integer := 5;
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comm_width_g : integer := 5;
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conf_file_g : string := "test_rx.txt"; -- File that contains parameters for expected incoming data
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conf_file_g : string := "test_rx.txt"; -- File that contains parameters for expected incoming data
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data_width_g : integer := 32
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data_width_g : integer := 32
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);
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);
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port (
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port (
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-- Interface: clock
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-- Interface: clock
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clk : in std_logic;
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clk : in std_logic;
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-- Interface: hibi_master
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-- Interface: hibi_master
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-- Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
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-- Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
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agent_re_out : out std_logic;
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agent_re_out : out std_logic;
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-- Interface: hibi_slave
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-- Interface: hibi_slave
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agent_av_in : in std_logic;
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agent_av_in : in std_logic;
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agent_comm_in : in std_logic_vector(4 downto 0);
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agent_comm_in : in std_logic_vector(4 downto 0);
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agent_data_in : in std_logic_vector(31 downto 0);
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agent_data_in : in std_logic_vector(31 downto 0);
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agent_empty_in : in std_logic;
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agent_empty_in : in std_logic;
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agent_one_d_in : in std_logic;
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agent_one_d_in : in std_logic;
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-- These ports are not in any interface
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-- These ports are not in any interface
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-- done_out : out std_logic;
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-- done_out : out std_logic;
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-- Interface: reset
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-- Interface: reset
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rst_n : in std_logic -- Active low
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rst_n : in std_logic -- Active low
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);
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);
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end component;
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end component;
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-- Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data.
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-- Simple unit for sending test data. There are separate units for transmitting (tx) and receiving (rx). This one sends commands to the tested IP (e.g. via HIBI). The other unit can then check the returned data.
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--
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--
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-- This IP-XACT component is fixed to 32-bit data and 5-bit command.
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-- This IP-XACT component is fixed to 32-bit data and 5-bit command.
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--
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--
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-- Works only in simulation because configuration is done with ASCII file.
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-- Works only in simulation because configuration is done with ASCII file.
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component basic_tester_tx
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component basic_tester_tx
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generic (
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generic (
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comm_width_g : integer := 5;
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comm_width_g : integer := 5;
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conf_file_g : string := "test_tx.txt"; -- File that contains the sent data
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conf_file_g : string := "test_tx.txt"; -- File that contains the sent data
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data_width_g : integer := 32
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data_width_g : integer := 32
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);
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);
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port (
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port (
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-- Interface: clock
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-- Interface: clock
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clk : in std_logic;
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clk : in std_logic;
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-- Interface: hibi_master
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-- Interface: hibi_master
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-- Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
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-- Tester sends data via this port. Regular and hi-prior data muxed. Addr and data muxed also.
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agent_av_out : out std_logic;
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agent_av_out : out std_logic;
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agent_comm_out : out std_logic_vector(4 downto 0);
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agent_comm_out : out std_logic_vector(4 downto 0);
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agent_data_out : out std_logic_vector(31 downto 0);
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agent_data_out : out std_logic_vector(31 downto 0);
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agent_we_out : out std_logic;
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agent_we_out : out std_logic;
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-- Interface: hibi_slave
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-- Interface: hibi_slave
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agent_full_in : in std_logic;
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agent_full_in : in std_logic;
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agent_one_p_in : in std_logic;
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agent_one_p_in : in std_logic;
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-- These ports are not in any interface
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-- These ports are not in any interface
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-- done_out : out std_logic;
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-- done_out : out std_logic;
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-- Interface: reset
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-- Interface: reset
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rst_n : in std_logic -- Active low
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rst_n : in std_logic -- Active low
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);
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);
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end component;
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end component;
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component hibi_segment
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component hibi_segment
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generic (
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generic (
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hibi_addr_0_g : integer := 16#01000000#; -- HIBI address for interface 0
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ip_mslave_0_addr_end : integer := 2; -- HIBI end address for interface 0
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hibi_addr_1_g : integer := 16#03000000#; -- HIBI address for interface 1
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ip_mslave_0_addr_start : integer := 1; -- HIBI address for interface 0
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hibi_addr_2_g : integer := 16#05000000#; -- HIBI address for interface 2
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ip_mslave_1_addr_end : integer := 4; -- HIBI end address for interface 1
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hibi_addr_3_g : integer := 16#07000000# -- HIBI address for interface 3
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ip_mslave_1_addr_start : integer := 3; -- HIBI address for interface 1
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ip_mslave_2_addr_end : integer := 6; -- HIBI end address for interface 2
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ip_mslave_2_addr_start : integer := 5; -- HIBI address for interface 2
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ip_mslave_3_addr_end : integer := 8; -- HIBI end address for interface 3
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ip_mslave_3_addr_start : integer := 7 -- HIBI address for interface 3
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);
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);
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port (
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port (
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-- Interface: clocks_0
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-- Interface: clocks_0
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-- Clock inputs interface for hibi wrapper_3
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-- Clock inputs interface for hibi wrapper_3
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agent_clk : in std_logic;
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agent_clk : in std_logic;
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agent_sync_clk : in std_logic;
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agent_sync_clk : in std_logic;
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bus_clk : in std_logic;
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bus_clk : in std_logic;
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bus_sync_clk : in std_logic;
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bus_sync_clk : in std_logic;
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-- Interface: clocks_1
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-- Interface: clocks_1
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-- Clock inputs interface for hibi wrapper_3
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-- Clock inputs interface for hibi wrapper_3
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agent_clk_1 : in std_logic;
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agent_clk_1 : in std_logic;
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agent_sync_clk_1 : in std_logic;
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agent_sync_clk_1 : in std_logic;
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bus_clk_1 : in std_logic;
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bus_clk_1 : in std_logic;
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bus_sync_clk_1 : in std_logic;
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bus_sync_clk_1 : in std_logic;
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-- Interface: clocks_2
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-- Interface: clocks_2
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-- Clock inputs interface for hibi wrapper_3
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-- Clock inputs interface for hibi wrapper_3
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-- agent_clk_2 : in std_logic;
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agent_clk_2 : in std_logic;
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-- agent_sync_clk_2 : in std_logic;
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agent_sync_clk_2 : in std_logic;
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-- bus_clk_2 : in std_logic;
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bus_clk_2 : in std_logic;
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bus_sync_clk_2 : in std_logic;
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bus_sync_clk_2 : in std_logic;
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-- Interface: clocks_3
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-- Interface: clocks_3
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-- Clock inputs interface for hibi wrapper_3
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-- Clock inputs interface for hibi wrapper_3
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-- agent_clk_3 : in std_logic;
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agent_clk_3 : in std_logic;
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-- agent_sync_clk_3 : in std_logic;
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agent_sync_clk_3 : in std_logic;
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-- bus_clk_3 : in std_logic;
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bus_clk_3 : in std_logic;
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bus_sync_clk_3 : in std_logic;
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bus_sync_clk_3 : in std_logic;
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-- Interface: ip_mMaster_0
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-- Interface: ip_mMaster_0
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-- HIBI ip mirrored master agent interface 0 (r4 wrapper)
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-- HIBI ip mirrored master agent interface 0 (r4 wrapper)
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agent_av_in : in std_logic;
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agent_av_in : in std_logic;
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agent_comm_in : in std_logic_vector(4 downto 0);
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agent_comm_in : in std_logic_vector(4 downto 0);
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agent_data_in : in std_logic_vector(31 downto 0);
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agent_data_in : in std_logic_vector(31 downto 0);
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agent_re_in : in std_logic;
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agent_re_in : in std_logic;
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agent_we_in : in std_logic;
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agent_we_in : in std_logic;
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-- Interface: ip_mMaster_1
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-- Interface: ip_mMaster_1
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-- HIBI ip mirrored master agent interface 1 (r4 wrapper)
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-- HIBI ip mirrored master agent interface 1 (r4 wrapper)
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agent_av_in_1 : in std_logic;
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agent_av_in_1 : in std_logic;
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agent_comm_in_1 : in std_logic_vector(4 downto 0);
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agent_comm_in_1 : in std_logic_vector(4 downto 0);
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agent_data_in_1 : in std_logic_vector(31 downto 0);
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agent_data_in_1 : in std_logic_vector(31 downto 0);
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agent_re_in_1 : in std_logic;
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agent_re_in_1 : in std_logic;
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agent_we_in_1 : in std_logic;
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agent_we_in_1 : in std_logic;
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-- Interface: ip_mMaster_2
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-- Interface: ip_mMaster_2
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-- HIBI ip mirrored master agent interface 2 (r4 wrapper)
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-- HIBI ip mirrored master agent interface 2 (r4 wrapper)
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agent_av_in_2 : in std_logic;
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agent_av_in_2 : in std_logic;
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agent_comm_in_2 : in std_logic_vector(4 downto 0);
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agent_comm_in_2 : in std_logic_vector(4 downto 0);
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agent_data_in_2 : in std_logic_vector(31 downto 0);
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agent_data_in_2 : in std_logic_vector(31 downto 0);
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agent_re_in_2 : in std_logic;
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agent_re_in_2 : in std_logic;
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agent_we_in_2 : in std_logic;
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agent_we_in_2 : in std_logic;
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-- Interface: ip_mMaster_3
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-- Interface: ip_mMaster_3
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-- HIBI ip mirrored master agent interface 3 (r4 wrapper)
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-- HIBI ip mirrored master agent interface 3 (r4 wrapper)
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agent_av_in_3 : in std_logic;
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agent_av_in_3 : in std_logic;
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agent_comm_in_3 : in std_logic_vector(4 downto 0);
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agent_comm_in_3 : in std_logic_vector(4 downto 0);
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agent_data_in_3 : in std_logic_vector(31 downto 0);
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agent_data_in_3 : in std_logic_vector(31 downto 0);
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agent_re_in_3 : in std_logic;
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agent_re_in_3 : in std_logic;
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agent_we_in_3 : in std_logic;
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agent_we_in_3 : in std_logic;
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-- Interface: ip_mSlave_0
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-- Interface: ip_mSlave_0
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-- HIBI ip mirrored slave agent interface 0 (r4 wrapper)
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-- HIBI ip mirrored slave agent interface 0 (r4 wrapper)
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-- agent_av_out : out std_logic;
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-- agent_av_out : out std_logic;
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-- agent_comm_out : out std_logic_vector(4 downto 0);
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-- agent_comm_out : out std_logic_vector(4 downto 0);
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-- agent_data_out : out std_logic_vector(31 downto 0);
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-- agent_data_out : out std_logic_vector(31 downto 0);
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-- agent_empty_out : out std_logic;
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-- agent_empty_out : out std_logic;
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agent_full_out : out std_logic;
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agent_full_out : out std_logic;
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-- agent_one_d_out : out std_logic;
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-- agent_one_d_out : out std_logic;
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agent_one_p_out : out std_logic;
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agent_one_p_out : out std_logic;
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-- Interface: ip_mSlave_1
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-- Interface: ip_mSlave_1
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-- HIBI ip mirrored slave agent interface 1 (r4 wrapper)
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-- HIBI ip mirrored slave agent interface 1 (r4 wrapper)
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agent_av_out_1 : out std_logic;
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agent_av_out_1 : out std_logic;
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agent_comm_out_1 : out std_logic_vector(4 downto 0);
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agent_comm_out_1 : out std_logic_vector(4 downto 0);
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agent_data_out_1 : out std_logic_vector(31 downto 0);
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agent_data_out_1 : out std_logic_vector(31 downto 0);
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agent_empty_out_1 : out std_logic;
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agent_empty_out_1 : out std_logic;
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-- agent_full_out_1 : out std_logic;
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-- agent_full_out_1 : out std_logic;
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agent_one_d_out_1 : out std_logic;
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agent_one_d_out_1 : out std_logic;
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-- agent_one_p_out_1 : out std_logic;
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-- agent_one_p_out_1 : out std_logic;
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|
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-- Interface: ip_mSlave_2
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-- Interface: ip_mSlave_2
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-- HIBI ip mirrored slave agent interface 2 (r4 wrapper)
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-- HIBI ip mirrored slave agent interface 2 (r4 wrapper)
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-- agent_av_out_2 : out std_logic;
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-- agent_av_out_2 : out std_logic;
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-- agent_comm_out_2 : out std_logic_vector(4 downto 0);
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-- agent_comm_out_2 : out std_logic_vector(4 downto 0);
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-- agent_data_out_2 : out std_logic_vector(31 downto 0);
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-- agent_data_out_2 : out std_logic_vector(31 downto 0);
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-- agent_empty_out_2 : out std_logic;
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-- agent_empty_out_2 : out std_logic;
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-- agent_full_out_2 : out std_logic;
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-- agent_full_out_2 : out std_logic;
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-- agent_one_d_out_2 : out std_logic;
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-- agent_one_d_out_2 : out std_logic;
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-- agent_one_p_out_2 : out std_logic;
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-- agent_one_p_out_2 : out std_logic;
|
|
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-- Interface: ip_mSlave_3
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-- Interface: ip_mSlave_3
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-- HIBI ip mirrored slave agent interface_3 (r4 wrapper)
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-- HIBI ip mirrored slave agent interface_3 (r4 wrapper)
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-- agent_av_out_3 : out std_logic;
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-- agent_av_out_3 : out std_logic;
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-- agent_comm_out_3 : out std_logic_vector(4 downto 0);
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-- agent_comm_out_3 : out std_logic_vector(4 downto 0);
|
-- agent_data_out_3 : out std_logic_vector(31 downto 0);
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-- agent_data_out_3 : out std_logic_vector(31 downto 0);
|
-- agent_empty_out_3 : out std_logic;
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-- agent_empty_out_3 : out std_logic;
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-- agent_full_out_3 : out std_logic;
|
-- agent_full_out_3 : out std_logic;
|
-- agent_one_d_out_3 : out std_logic;
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-- agent_one_d_out_3 : out std_logic;
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-- agent_one_p_out_3 : out std_logic;
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-- agent_one_p_out_3 : out std_logic;
|
|
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-- Interface: rst_n
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-- Interface: rst_n
|
-- Active low reset interface.
|
-- Active low reset interface.
|
rst_n : in std_logic
|
rst_n : in std_logic
|
|
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Simple clock generator dor simulation.
|
-- Simple clock generator dor simulation.
|
component clk_gen
|
component clk_gen
|
generic (
|
generic (
|
hi_period_ns_g : integer := 1;
|
hi_period_ns_g : integer := 1;
|
lo_period_ns_g : integer := 1
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lo_period_ns_g : integer := 1
|
|
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);
|
);
|
port (
|
port (
|
|
|
-- There ports are contained in many interfaces
|
-- There ports are contained in many interfaces
|
clk_out : out std_logic
|
clk_out : out std_logic
|
|
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Simple active-low reset signal generator dor simulation
|
-- Simple active-low reset signal generator dor simulation
|
component rst_gen
|
component rst_gen
|
generic (
|
generic (
|
active_period_ns_g : integer := 100
|
active_period_ns_g : integer := 100
|
|
|
);
|
);
|
port (
|
port (
|
|
|
-- Interface: Generated_reset
|
-- Interface: Generated_reset
|
rst_n_out : out std_logic
|
rst_n_out : out std_logic
|
|
|
);
|
);
|
end component;
|
end component;
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- You can write vhdl code after this tag and it is saved through the generator.
|
-- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
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-- Stop writing your code after this tag.
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-- Stop writing your code after this tag.
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begin
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begin
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|
|
-- You can write vhdl code after this tag and it is saved through the generator.
|
-- You can write vhdl code after this tag and it is saved through the generator.
|
-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
|
-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
|
-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
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-- Stop writing your code after this tag.
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-- Stop writing your code after this tag.
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basic_tester_rx_0 : basic_tester_rx
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basic_tester_rx_0 : basic_tester_rx
|
generic map (
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generic map (
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conf_file_g => "test_rx.txt"
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conf_file_g => "test_rx.txt"
|
)
|
)
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port map (
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port map (
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agent_av_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
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agent_av_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
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agent_comm_in(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
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agent_comm_in(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
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agent_data_in(31 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA(31 downto 0),
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agent_data_in(31 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA(31 downto 0),
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agent_empty_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
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agent_empty_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
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agent_one_d_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
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agent_one_d_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
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agent_re_out => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
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agent_re_out => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
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clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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rst_n => rst_r_nRESETn
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rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
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);
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);
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basic_tester_tx_0 : basic_tester_tx
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basic_tester_tx_0 : basic_tester_tx
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generic map (
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generic map (
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conf_file_g => "test_tx.txt"
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conf_file_g => "test_tx.txt"
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)
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)
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port map (
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port map (
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agent_av_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
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agent_av_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
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agent_comm_out(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
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agent_comm_out(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
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agent_data_out(31 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA(31 downto 0),
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agent_data_out(31 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA(31 downto 0),
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agent_full_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
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agent_full_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
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agent_one_p_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
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agent_one_p_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
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agent_we_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
|
agent_we_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
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clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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rst_n => rst_r_nRESETn
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rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
|
);
|
);
|
|
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clk_gen_0 : clk_gen
|
clk_gen_0 : clk_gen
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port map (
|
port map (
|
clk_out => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK
|
clk_out => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK
|
);
|
);
|
|
|
hibi_segment_0 : hibi_segment(structural)
|
hibi_segment_0 : hibi_segment
|
generic map (
|
|
hibi_addr_0_g => 16#07000000#,
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|
hibi_addr_1_g => 16#05000000#,
|
|
hibi_addr_2_g => 16#03000000#,
|
|
hibi_addr_3_g => 16#01000000#
|
|
)
|
|
port map (
|
port map (
|
agent_av_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
|
agent_av_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
|
agent_av_in_1 => '0',
|
agent_av_in_1 => '0',
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agent_av_in_2 => '0',
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agent_av_in_2 => '0',
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agent_av_in_3 => '0',
|
agent_av_in_3 => '0',
|
agent_av_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
|
agent_av_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
|
agent_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
agent_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
agent_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
agent_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
|
agent_clk_2 => '0',
|
|
agent_clk_3 => '0',
|
agent_comm_in(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
|
agent_comm_in(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
|
agent_comm_in_1 => (others => '0'),
|
agent_comm_in_1 => (others => '0'),
|
agent_comm_in_2 => (others => '0'),
|
agent_comm_in_2 => (others => '0'),
|
agent_comm_in_3 => (others => '0'),
|
agent_comm_in_3 => (others => '0'),
|
agent_comm_out_1(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
|
agent_comm_out_1(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
|
agent_data_in(31 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA(31 downto 0),
|
agent_data_in(31 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA(31 downto 0),
|
agent_data_in_1 => (others => '0'),
|
agent_data_in_1 => (others => '0'),
|
agent_data_in_2 => (others => '0'),
|
agent_data_in_2 => (others => '0'),
|
agent_data_in_3 => (others => '0'),
|
agent_data_in_3 => (others => '0'),
|
agent_data_out_1(31 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA(31 downto 0),
|
agent_data_out_1(31 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA(31 downto 0),
|
agent_empty_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
|
agent_empty_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
|
agent_full_out => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
|
agent_full_out => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
|
agent_one_d_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
|
agent_one_d_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
|
agent_one_p_out => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
|
agent_one_p_out => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
|
agent_re_in => '0',
|
agent_re_in => '0',
|
agent_re_in_1 => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
|
agent_re_in_1 => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
|
agent_re_in_2 => '0',
|
agent_re_in_2 => '0',
|
agent_re_in_3 => '0',
|
agent_re_in_3 => '0',
|
agent_sync_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
agent_sync_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
agent_sync_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
agent_sync_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
|
agent_sync_clk_2 => '0',
|
|
agent_sync_clk_3 => '0',
|
agent_we_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
|
agent_we_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
|
agent_we_in_1 => '0',
|
agent_we_in_1 => '0',
|
agent_we_in_2 => '0',
|
agent_we_in_2 => '0',
|
agent_we_in_3 => '0',
|
agent_we_in_3 => '0',
|
bus_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
bus_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
bus_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
bus_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
bus_sync_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
bus_clk_2 => '0',
|
bus_sync_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
|
bus_clk_3 => '0',
|
|
bus_sync_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
|
bus_sync_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
|
bus_sync_clk_2 => '0',
|
bus_sync_clk_2 => '0',
|
bus_sync_clk_3 => '0',
|
bus_sync_clk_3 => '0',
|
rst_n => rst_r_nRESETn
|
rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
|
);
|
);
|
|
|
rst_gen_0 : rst_gen
|
rst_gen_0 : rst_gen
|
port map (
|
port map (
|
rst_n_out => rst_r_nRESETn
|
rst_n_out => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
|
);
|
);
|
|
|
end structural_seg;
|
end structural_seg;
|
|
|
|
|
