URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 147 |
Rev 157 |
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TUT
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TUT
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soc
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soc
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de2_samos_soc
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de2_samos_soc
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1.0
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1.0
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Altera de2 template soc
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Altera de2 template soc
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rst_n
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rst_n
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false
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false
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RESETn
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RESETn
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0
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0
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0
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0
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SW_17
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SW_17
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0
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0
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0
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0
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8
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8
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little
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little
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sram_if
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false
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SRAM_ADDR_FROM_SRAM
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17
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0
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SRAM_ADDR
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17
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0
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SRAM_CE_N_FROM_SRAM
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0
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0
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SRAM_CE_N
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0
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0
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SRAM_DQ_TO_AND_FROM_SRAM
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15
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0
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SRAM_DQ
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15
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0
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SRAM_LB_N_FROM_SRAM
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0
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0
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SRAM_LB_N
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0
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0
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SRAM_OE_N_FROM_SRAM
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0
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0
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SRAM_OE_N
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0
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0
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SRAM_UB_N_FROM_SRAM
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0
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0
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SRAM_UB_N
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0
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0
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SRAM_WE_N_FROM_SRAM
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0
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0
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SRAM_WE_N
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0
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0
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8
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little
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DM9000A
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DM9000A
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false
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false
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eth_clk_out
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eth_clk_out
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0
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0
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0
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0
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ENET_CLK
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ENET_CLK
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0
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0
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0
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0
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eth_chip_sel_out
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eth_chip_sel_out
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0
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0
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0
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0
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ENET_CS_N
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ENET_CS_N
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0
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0
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0
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0
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eth_cmd_out
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eth_cmd_out
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0
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0
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0
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0
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ENET_CMD
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ENET_CMD
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0
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0
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0
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0
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eth_data_inout
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eth_data_inout
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15
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15
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0
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0
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ENET_DATA
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ENET_DATA
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15
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15
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0
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0
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eth_interrupt_in
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eth_interrupt_in
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0
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0
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0
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0
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ENET_INT
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ENET_INT
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0
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0
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0
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0
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eth_read_out
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eth_read_out
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0
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0
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0
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0
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ENET_RD_N
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ENET_RD_N
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0
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0
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0
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0
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eth_reset_out
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eth_reset_out
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0
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0
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0
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0
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ENET_RST_N
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ENET_RST_N
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0
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0
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0
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0
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eth_write_out
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eth_write_out
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0
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0
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0
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0
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ENET_WR_N
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ENET_WR_N
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0
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0
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0
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0
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8
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8
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little
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little
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clk_in
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clk_in
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false
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false
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CLK
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CLK
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0
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0
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0
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0
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CLOCK_50
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CLOCK_50
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0
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0
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0
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0
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8
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8
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little
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little
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sdram_clk
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sdram_clk
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false
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false
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CLK
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CLK
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0
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0
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0
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0
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DRAM_CLK
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DRAM_CLK
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0
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0
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0
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0
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8
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8
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little
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little
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sdram_if
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sdram_if
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false
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false
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sdram_address_out
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sdram_address_out
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11
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11
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0
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0
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DRAM_ADDR
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DRAM_ADDR
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11
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11
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0
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0
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sdram_ba_out
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sdram_ba_out
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1
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1
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0
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0
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DRAM_BA
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DRAM_BA
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1
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1
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0
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0
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sdram_cas_n_out
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sdram_cas_n_out
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0
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0
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0
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0
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DRAM_CAS_N
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DRAM_CAS_N
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0
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0
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0
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0
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sdram_cke_out
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sdram_cke_out
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0
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0
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0
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0
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DRAM_CKE
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DRAM_CKE
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0
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0
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0
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0
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sdram_cs_n_out
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sdram_cs_n_out
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0
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0
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0
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0
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DRAM_CS_N
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DRAM_CS_N
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0
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0
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0
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0
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sdram_data_inout
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sdram_data_inout
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15
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15
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0
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0
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DRAM_DQ
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DRAM_DQ
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15
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15
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0
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0
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sdram_dqm_out
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sdram_dqm_out
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1
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1
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0
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0
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DRAM_DQM
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DRAM_DQM
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1
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1
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0
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0
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sdram_ras_n_out
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sdram_ras_n_out
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0
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0
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0
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0
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DRAM_RAS_N
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DRAM_RAS_N
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0
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0
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0
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0
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sdram_we_n_out
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sdram_we_n_out
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0
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0
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0
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0
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DRAM_WE_N
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DRAM_WE_N
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0
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0
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8
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little
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sram_if
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false
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SRAM_ADDR_FROM_SRAM
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17
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0
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SRAM_ADDR
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17
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0
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SRAM_CE_N_FROM_SRAM
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0
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0
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SRAM_CE_N
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0
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0
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SRAM_DQ_TO_AND_FROM_SRAM
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15
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0
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SRAM_DQ
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15
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0
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SRAM_LB_N_FROM_SRAM
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0
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0
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SRAM_LB_N
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0
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0
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SRAM_OE_N_FROM_SRAM
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0
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0
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SRAM_OE_N
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0
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0
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SRAM_UB_N_FROM_SRAM
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0
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0
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SRAM_UB_N
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0
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0
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SRAM_WE_N_FROM_SRAM
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0
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0
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SRAM_WE_N
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0
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0
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0
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0
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8
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8
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little
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little
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rtl
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rtl
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::
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::
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structural
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structural
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structural_vhd
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structural_vhd
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acc_only
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acc_only
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structural_vhd
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structural_vhd
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VHDL:Kactus2:
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VHDL:Kactus2:
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vhdl
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vhdl
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de2_samos_soc(structural)
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de2_samos_soc(structural)
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structural_vhdlSource
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structural_vhdlSource
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CLOCK_50
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CLOCK_50
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in
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in
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0
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0
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0
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0
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DRAM_ADDR
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DRAM_ADDR
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out
|
out
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11
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11
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0
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0
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DRAM_BA
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DRAM_BA
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out
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out
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1
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1
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0
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0
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DRAM_CAS_N
|
DRAM_CAS_N
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out
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out
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0
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0
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0
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0
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DRAM_CKE
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DRAM_CKE
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out
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out
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0
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0
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0
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0
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DRAM_CLK
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DRAM_CLK
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out
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out
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0
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0
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0
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0
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DRAM_CS_N
|
DRAM_CS_N
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out
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out
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0
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0
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0
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0
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DRAM_DQ
|
DRAM_DQ
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inout
|
inout
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15
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15
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0
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0
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DRAM_DQM
|
DRAM_DQM
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out
|
out
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1
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1
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0
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0
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DRAM_RAS_N
|
DRAM_RAS_N
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out
|
out
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0
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0
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0
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0
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DRAM_WE_N
|
DRAM_WE_N
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out
|
out
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0
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0
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0
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0
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SRAM_ADDR
|
SRAM_ADDR
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out
|
out
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17
|
17
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0
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0
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SRAM_CE_N
|
SRAM_CE_N
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out
|
out
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0
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0
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0
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0
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SRAM_DQ
|
SRAM_DQ
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inout
|
inout
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15
|
15
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0
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0
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SRAM_LB_N
|
SRAM_LB_N
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out
|
out
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0
|
0
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0
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0
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SRAM_OE_N
|
SRAM_OE_N
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out
|
out
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0
|
0
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0
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0
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SRAM_UB_N
|
SRAM_UB_N
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out
|
out
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0
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0
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0
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0
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SRAM_WE_N
|
SRAM_WE_N
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out
|
out
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0
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0
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0
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0
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SW_17
|
SW_17
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in
|
in
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0
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0
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0
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0
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ENET_CLK
|
ENET_CLK
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out
|
out
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0
|
0
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0
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0
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ENET_CMD
|
ENET_CMD
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out
|
out
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0
|
0
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0
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0
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ENET_CS_N
|
ENET_CS_N
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out
|
out
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0
|
0
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0
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0
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ENET_DATA
|
ENET_DATA
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inout
|
inout
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15
|
15
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0
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0
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ENET_INT
|
ENET_INT
|
|
|
in
|
in
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
ENET_RD_N
|
ENET_RD_N
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
ENET_RST_N
|
ENET_RST_N
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
ENET_WR_N
|
ENET_WR_N
|
|
|
out
|
out
|
|
|
0
|
0
|
0
|
0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
quartusSettings
|
quartusSettings
|
|
|
pin_mappings/de2.qsf
|
pin_mappings/de2.qsf
|
quartusPinmap
|
quartusPinmap
|
false
|
false
|
|
|
|
|
|
|
structural_vhdlSource
|
structural_vhdlSource
|
sourceFiles
|
sourceFiles
|
|
|
de2_samos_soc.vhd
|
de2_samos_soc.vhd
|
vhdlSource
|
vhdlSource
|
true
|
true
|
work
|
work
|
|
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
|
|
vhdlSource
|
vhdlSource
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
vhdlSource-87
|
vhdlSource-87
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
vhdlSource-93
|
vhdlSource-93
|
vcom
|
vcom
|
-quiet -check_synthesis -work work
|
-quiet -check_synthesis -work work
|
true
|
true
|
|
|
|
|
|
|
|
|
|
|
|
|
SoC
|
SoC
|
HW
|
HW
|
Template
|
Template
|
|
|
|
|
|
|
|
|
|
|
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