-- ***************************************************
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-- ***************************************************
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-- File: udp_flood_example_dm9000a.vhd
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-- File: udp_flood_example_dm9000a.vhd
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-- Creation date: 05.04.2012
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-- Creation date: 18.01.2013
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-- Creation time: 13:38:38
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-- Creation time: 12:46:22
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-- Description: Simple example to test the connection FPGA -> PC.
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-- Description: Simple example to test the connection FPGA -> PC.
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--
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--
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-- Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
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-- Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
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-- Created by: ege
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-- Created by: matilail
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-- This file was generated with Kactus2 vhdl generator.
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-- This file was generated with Kactus2 vhdl generator.
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-- ***************************************************
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-- ***************************************************
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library IEEE;
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library IEEE;
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library work;
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library work;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.all;
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use work.all;
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entity udp_flood_example_dm9000a is
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entity udp_flood_example_dm9000a is
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port (
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port (
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-- Interface: clk_in
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-- Interface: clk_in
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-- Clock input.
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-- Clock input.
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clk_in_CLK : in std_logic;
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clk_in_CLK : in std_logic;
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-- Interface: DM9000A
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-- Interface: DM9000A
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-- Connection to DM9000A chip (Ethernet PHY) found e.g. in DE2 board. Expects 25 MHz clock.
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-- Connection to DM9000A chip (Ethernet PHY) found e.g. in DE2 board. Expects 25 MHz clock.
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DM9000A_eth_interrupt_in : in std_logic;
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DM9000A_eth_interrupt_in : in std_logic;
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DM9000A_eth_chip_sel_out : out std_logic;
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DM9000A_eth_chip_sel_out : out std_logic;
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DM9000A_eth_clk_out : out std_logic;
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DM9000A_eth_clk_out : out std_logic;
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DM9000A_eth_cmd_out : out std_logic;
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DM9000A_eth_cmd_out : out std_logic;
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DM9000A_eth_read_out : out std_logic;
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DM9000A_eth_read_out : out std_logic;
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DM9000A_eth_reset_out : out std_logic;
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DM9000A_eth_reset_out : out std_logic;
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DM9000A_eth_write_out : out std_logic;
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DM9000A_eth_write_out : out std_logic;
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DM9000A_eth_data_inout : inout std_logic_vector(15 downto 0);
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DM9000A_eth_data_inout : inout std_logic_vector(15 downto 0);
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-- Interface: link_up_out
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-- Interface: link_up_out
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-- 1-bit status
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-- 1-bit status
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link_up_out_gpio_out : out std_logic;
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link_up_out_gpio_out : out std_logic;
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-- Interface: rst_n
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-- Interface: rst_n
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-- Active-low reset
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-- Active-low reset
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rst_n_RESETn : in std_logic
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rst_n_RESETn : in std_logic
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);
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);
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end udp_flood_example_dm9000a;
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end udp_flood_example_dm9000a;
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architecture kactusHierarchical of udp_flood_example_dm9000a is
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architecture kactusHierarchical of udp_flood_example_dm9000a is
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signal pll_flooderCLK : std_logic;
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signal pll_flooderCLK : std_logic;
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signal udp_flooderrxdest_port_out : std_logic_vector(15 downto 0);
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signal udp_flooderrxdest_port_out : std_logic_vector(15 downto 0);
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signal floodertx_udpfatal_error_out : std_logic;
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signal floodertx_udpfatal_error_out : std_logic;
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signal floodertx_udplink_up_out : std_logic;
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signal floodertx_udplink_up_out : std_logic;
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signal udp_flooderrxnew_rx_out : std_logic;
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signal udp_flooderrxnew_rx_out : std_logic;
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signal floodertx_udpnew_tx_in : std_logic;
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signal floodertx_udpnew_tx_in : std_logic;
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signal floodertx_udpno_arp_target_MAC_in : std_logic_vector(47 downto 0);
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signal floodertx_udpno_arp_target_MAC_in : std_logic_vector(47 downto 0);
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signal udp_flooderrxrx_data_out : std_logic_vector(15 downto 0);
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signal udp_flooderrxrx_data_out : std_logic_vector(15 downto 0);
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signal udp_flooderrxrx_data_valid_out : std_logic;
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signal udp_flooderrxrx_data_valid_out : std_logic;
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signal udp_flooderrxrx_erroneous_out : std_logic;
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signal udp_flooderrxrx_erroneous_out : std_logic;
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signal udp_flooderrxrx_error_out : std_logic;
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signal udp_flooderrxrx_error_out : std_logic;
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signal udp_flooderrxrx_len_out : std_logic_vector(10 downto 0);
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signal udp_flooderrxrx_len_out : std_logic_vector(10 downto 0);
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signal udp_flooderrxrx_re_in : std_logic;
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signal udp_flooderrxrx_re_in : std_logic;
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signal udp_flooderrxsource_addr_out : std_logic_vector(31 downto 0);
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signal udp_flooderrxsource_addr_out : std_logic_vector(31 downto 0);
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signal udp_flooderrxsource_port_out : std_logic_vector(15 downto 0);
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signal udp_flooderrxsource_port_out : std_logic_vector(15 downto 0);
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signal floodertx_udpsource_port_in : std_logic_vector(15 downto 0);
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signal floodertx_udpsource_port_in : std_logic_vector(15 downto 0);
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signal floodertx_udptarget_addr_in : std_logic_vector(31 downto 0);
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signal floodertx_udptarget_addr_in : std_logic_vector(31 downto 0);
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signal floodertx_udptarget_port_in : std_logic_vector(15 downto 0);
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signal floodertx_udptarget_port_in : std_logic_vector(15 downto 0);
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signal floodertx_udptx_data_in : std_logic_vector(15 downto 0);
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signal floodertx_udptx_data_in : std_logic_vector(15 downto 0);
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signal floodertx_udptx_data_valid_in : std_logic;
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signal floodertx_udptx_data_valid_in : std_logic;
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signal floodertx_udptx_len_in : std_logic_vector(10 downto 0);
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signal floodertx_udptx_len_in : std_logic_vector(10 downto 0);
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signal floodertx_udptx_re_out : std_logic;
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signal floodertx_udptx_re_out : std_logic;
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-- Connect to UDP/IP controller. Creates TX operations as quickly as possible. Sends running numbers.
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-- Connect to UDP/IP controller. Creates TX operations as quickly as possible. Sends running numbers.
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-- Destination and packet size are configurable by using generics.
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-- Destination and packet size are configurable by using generics.
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component simple_udp_flood_example
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component simple_udp_flood_example
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generic (
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generic (
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data_width_g : integer := 16;
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data_width_g : integer := 16;
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disable_arp_g : integer := 0;
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disable_arp_g : integer := 0;
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packet_len_g : integer := 1000;
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packet_len_g : integer := 1000;
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source_ip_port_g : integer := 6000;
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source_ip_port_g : integer := 6000;
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target_MAC_addr_g : std_logic_vector(47 downto 0) := x"ACDCABBACD01";
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target_MAC_addr_g : std_logic_vector(47 downto 0) := x"ACDCABBACD01";
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target_ip_addr_g : std_logic_vector(31 downto 0) := x"0A000001";
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target_ip_addr_g : std_logic_vector(31 downto 0) := x"0A000001";
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target_ip_port_g : integer := 5000
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target_ip_port_g : integer := 5000
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);
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);
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port (
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port (
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-- Interface: clk
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-- Interface: clk
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-- Clock 25 MHz synchronous to UDP/IP/ETH clock.
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-- Clock 25 MHz synchronous to UDP/IP/ETH clock.
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clk : in std_logic;
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clk : in std_logic;
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-- Interface: link_up_out
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-- Interface: link_up_out
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-- Connect a LED here; rises a few seconds after the autonegotiation process is done.
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-- Connect a LED here; rises a few seconds after the autonegotiation process is done.
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link_up_out : out std_logic;
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link_up_out : out std_logic;
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-- Interface: rst_n
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-- Interface: rst_n
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-- rst_n
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-- rst_n
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rst_n : in std_logic;
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rst_n : in std_logic;
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-- There ports are contained in many interfaces
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-- There ports are contained in many interfaces
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fatal_error_in : in std_logic;
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fatal_error_in : in std_logic;
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link_up_in : in std_logic;
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link_up_in : in std_logic;
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-- Interface: udp_ip_rx
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-- Interface: udp_ip_rx
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-- Optional, this example flooder just accepts all incoming data but does nothing with it.
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-- Optional, this example flooder just accepts all incoming data but does nothing with it.
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dest_port_in : in std_logic_vector(15 downto 0);
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dest_port_in : in std_logic_vector(15 downto 0);
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new_rx_in : in std_logic;
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new_rx_in : in std_logic;
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rx_data_in : in std_logic_vector(15 downto 0);
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rx_data_in : in std_logic_vector(15 downto 0);
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rx_data_valid_in : in std_logic;
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rx_data_valid_in : in std_logic;
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rx_erroneous_in : in std_logic;
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rx_erroneous_in : in std_logic;
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rx_error_in : in std_logic;
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rx_error_in : in std_logic;
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rx_len_in : in std_logic_vector(10 downto 0);
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rx_len_in : in std_logic_vector(10 downto 0);
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source_addr_in : in std_logic_vector(31 downto 0);
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source_addr_in : in std_logic_vector(31 downto 0);
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source_port_in : in std_logic_vector(15 downto 0);
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source_port_in : in std_logic_vector(15 downto 0);
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rx_re_out : out std_logic;
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rx_re_out : out std_logic;
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-- Interface: udp_ip_tx
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-- Interface: udp_ip_tx
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-- Flooder sends
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-- Flooder sends
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tx_re_in : in std_logic;
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tx_re_in : in std_logic;
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new_tx_out : out std_logic;
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new_tx_out : out std_logic;
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no_arp_target_MAC_out : out std_logic_vector(47 downto 0);
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no_arp_target_MAC_out : out std_logic_vector(47 downto 0);
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source_port_out : out std_logic_vector(15 downto 0);
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source_port_out : out std_logic_vector(15 downto 0);
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target_addr_out : out std_logic_vector(31 downto 0);
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target_addr_out : out std_logic_vector(31 downto 0);
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target_port_out : out std_logic_vector(15 downto 0);
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target_port_out : out std_logic_vector(15 downto 0);
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tx_data_out : out std_logic_vector(15 downto 0);
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tx_data_out : out std_logic_vector(15 downto 0);
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tx_data_valid_out : out std_logic;
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tx_data_valid_out : out std_logic;
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tx_len_out : out std_logic_vector(10 downto 0)
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tx_len_out : out std_logic_vector(10 downto 0)
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);
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);
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end component;
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end component;
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-- DM9000A controller and UDP/IP.
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-- DM9000A controller and UDP/IP.
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component udp_ip_dm9000a
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component udp_ip_dm9000a
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generic (
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generic (
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disable_arp_g : integer := 0;
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disable_arp_g : integer := 0;
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disable_rx_g : integer := 0
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disable_rx_g : integer := 0
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);
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);
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port (
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port (
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-- Interface: app_rx
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-- Interface: app_rx
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-- Application receive operations
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-- Application receive operations
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rx_re_in : in std_logic;
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rx_re_in : in std_logic;
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dest_port_out : out std_logic_vector(15 downto 0);
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dest_port_out : out std_logic_vector(15 downto 0);
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new_rx_out : out std_logic;
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new_rx_out : out std_logic;
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rx_data_out : out std_logic_vector(15 downto 0);
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rx_data_out : out std_logic_vector(15 downto 0);
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rx_data_valid_out : out std_logic;
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rx_data_valid_out : out std_logic;
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rx_erroneous_out : out std_logic;
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rx_erroneous_out : out std_logic;
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rx_error_out : out std_logic;
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rx_error_out : out std_logic;
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rx_len_out : out std_logic_vector(10 downto 0);
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rx_len_out : out std_logic_vector(10 downto 0);
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source_addr_out : out std_logic_vector(31 downto 0);
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source_addr_out : out std_logic_vector(31 downto 0);
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source_port_out : out std_logic_vector(15 downto 0);
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source_port_out : out std_logic_vector(15 downto 0);
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-- Interface: app_tx
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-- Interface: app_tx
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-- Application transmit operations
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-- Application transmit operations
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new_tx_in : in std_logic;
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new_tx_in : in std_logic;
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no_arp_target_MAC_in : in std_logic_vector(47 downto 0);
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no_arp_target_MAC_in : in std_logic_vector(47 downto 0);
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source_port_in : in std_logic_vector(15 downto 0);
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source_port_in : in std_logic_vector(15 downto 0);
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target_addr_in : in std_logic_vector(31 downto 0);
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target_addr_in : in std_logic_vector(31 downto 0);
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target_port_in : in std_logic_vector(15 downto 0);
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target_port_in : in std_logic_vector(15 downto 0);
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tx_data_in : in std_logic_vector(15 downto 0);
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tx_data_in : in std_logic_vector(15 downto 0);
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tx_data_valid_in : in std_logic;
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tx_data_valid_in : in std_logic;
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tx_len_in : in std_logic_vector(10 downto 0);
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tx_len_in : in std_logic_vector(10 downto 0);
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tx_re_out : out std_logic;
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tx_re_out : out std_logic;
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-- Interface: clk
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-- Interface: clk
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-- Clock 25 MHz in.
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-- Clock 25 MHz in.
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clk : in std_logic;
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clk : in std_logic;
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-- Interface: DM9000A
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-- Interface: DM9000A
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-- Connection to the DM9000A chip via IO pins.
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-- Connection to the DM9000A chip via IO pins.
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eth_interrupt_in : in std_logic;
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eth_interrupt_in : in std_logic;
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eth_chip_sel_out : out std_logic;
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eth_chip_sel_out : out std_logic;
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eth_clk_out : out std_logic;
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eth_clk_out : out std_logic;
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eth_cmd_out : out std_logic;
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eth_cmd_out : out std_logic;
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eth_read_out : out std_logic;
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eth_read_out : out std_logic;
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eth_reset_out : out std_logic;
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eth_reset_out : out std_logic;
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eth_write_out : out std_logic;
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eth_write_out : out std_logic;
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eth_data_inout : inout std_logic_vector(15 downto 0);
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eth_data_inout : inout std_logic_vector(15 downto 0);
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-- Interface: rst_n
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-- Interface: rst_n
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-- Asynchronous reset active-low.
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-- Asynchronous reset active-low.
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rst_n : in std_logic;
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rst_n : in std_logic;
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-- There ports are contained in many interfaces
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-- There ports are contained in many interfaces
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fatal_error_out : out std_logic;
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fatal_error_out : out std_logic;
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link_up_out : out std_logic
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link_up_out : out std_logic
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);
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);
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end component;
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end component;
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-- 25 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 2)
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-- 25 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 2)
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component altera_de2_pll_25
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component altera_de2_pll_25
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port (
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port (
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-- Interface: clk_in
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-- Interface: clk_in
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-- Input clock (50 MHz, DE2 PIN_N2)
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-- Input clock (50 MHz, DE2 PIN_N2)
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inclk0 : in std_logic;
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inclk0 : in std_logic;
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-- Interface: clk_out
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-- Interface: clk_out
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-- Output clock: input clock divided by 2.
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-- Output clock: input clock divided by 2.
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c0 : out std_logic
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c0 : out std_logic
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);
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);
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end component;
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end component;
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
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-- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
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-- Stop writing your code after this tag.
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-- Stop writing your code after this tag.
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begin
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begin
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- You can write vhdl code after this tag and it is saved through the generator.
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
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-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
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-- Stop writing your code after this tag.
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-- Stop writing your code after this tag.
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altera_de2_pll_25_1 : altera_de2_pll_25
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altera_de2_pll_25_1 : altera_de2_pll_25
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port map (
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port map (
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c0 => pll_flooderCLK,
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c0 => pll_flooderCLK,
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inclk0 => clk_in_CLK
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inclk0 => clk_in_CLK
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);
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);
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simple_udp_flood_example_1 : simple_udp_flood_example
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simple_udp_flood_example_1 : simple_udp_flood_example
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port map (
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port map (
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clk => pll_flooderCLK,
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clk => pll_flooderCLK,
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dest_port_in(15 downto 0) => udp_flooderrxdest_port_out(15 downto 0),
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dest_port_in(15 downto 0) => udp_flooderrxdest_port_out(15 downto 0),
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fatal_error_in => floodertx_udpfatal_error_out,
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fatal_error_in => floodertx_udpfatal_error_out,
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link_up_in => floodertx_udplink_up_out,
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link_up_in => floodertx_udplink_up_out,
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link_up_out => link_up_out_gpio_out,
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link_up_out => link_up_out_gpio_out,
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new_rx_in => udp_flooderrxnew_rx_out,
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new_rx_in => udp_flooderrxnew_rx_out,
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new_tx_out => floodertx_udpnew_tx_in,
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new_tx_out => floodertx_udpnew_tx_in,
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no_arp_target_MAC_out(47 downto 0) => floodertx_udpno_arp_target_MAC_in(47 downto 0),
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no_arp_target_MAC_out(47 downto 0) => floodertx_udpno_arp_target_MAC_in(47 downto 0),
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rst_n => rst_n_RESETn,
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rst_n => rst_n_RESETn,
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rx_data_in(15 downto 0) => udp_flooderrxrx_data_out(15 downto 0),
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rx_data_in(15 downto 0) => udp_flooderrxrx_data_out(15 downto 0),
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rx_data_valid_in => udp_flooderrxrx_data_valid_out,
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rx_data_valid_in => udp_flooderrxrx_data_valid_out,
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rx_erroneous_in => udp_flooderrxrx_erroneous_out,
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rx_erroneous_in => udp_flooderrxrx_erroneous_out,
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rx_error_in => udp_flooderrxrx_error_out,
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rx_error_in => udp_flooderrxrx_error_out,
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rx_len_in(10 downto 0) => udp_flooderrxrx_len_out(10 downto 0),
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rx_len_in(10 downto 0) => udp_flooderrxrx_len_out(10 downto 0),
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rx_re_out => udp_flooderrxrx_re_in,
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rx_re_out => udp_flooderrxrx_re_in,
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source_addr_in(31 downto 0) => udp_flooderrxsource_addr_out(31 downto 0),
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source_addr_in(31 downto 0) => udp_flooderrxsource_addr_out(31 downto 0),
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source_port_in(15 downto 0) => udp_flooderrxsource_port_out(15 downto 0),
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source_port_in(15 downto 0) => udp_flooderrxsource_port_out(15 downto 0),
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source_port_out(15 downto 0) => floodertx_udpsource_port_in(15 downto 0),
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source_port_out(15 downto 0) => floodertx_udpsource_port_in(15 downto 0),
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target_addr_out(31 downto 0) => floodertx_udptarget_addr_in(31 downto 0),
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target_addr_out(31 downto 0) => floodertx_udptarget_addr_in(31 downto 0),
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target_port_out(15 downto 0) => floodertx_udptarget_port_in(15 downto 0),
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target_port_out(15 downto 0) => floodertx_udptarget_port_in(15 downto 0),
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tx_data_out(15 downto 0) => floodertx_udptx_data_in(15 downto 0),
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tx_data_out(15 downto 0) => floodertx_udptx_data_in(15 downto 0),
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tx_data_valid_out => floodertx_udptx_data_valid_in,
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tx_data_valid_out => floodertx_udptx_data_valid_in,
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tx_len_out(10 downto 0) => floodertx_udptx_len_in(10 downto 0),
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tx_len_out(10 downto 0) => floodertx_udptx_len_in(10 downto 0),
|
tx_re_in => floodertx_udptx_re_out
|
tx_re_in => floodertx_udptx_re_out
|
);
|
);
|
|
|
udp_ip_dm9000a_1 : udp_ip_dm9000a
|
udp_ip_dm9000a_1 : udp_ip_dm9000a
|
port map (
|
port map (
|
clk => pll_flooderCLK,
|
clk => pll_flooderCLK,
|
dest_port_out(15 downto 0) => udp_flooderrxdest_port_out(15 downto 0),
|
dest_port_out(15 downto 0) => udp_flooderrxdest_port_out(15 downto 0),
|
eth_chip_sel_out => DM9000A_eth_chip_sel_out,
|
eth_chip_sel_out => DM9000A_eth_chip_sel_out,
|
eth_clk_out => DM9000A_eth_clk_out,
|
eth_clk_out => DM9000A_eth_clk_out,
|
eth_cmd_out => DM9000A_eth_cmd_out,
|
eth_cmd_out => DM9000A_eth_cmd_out,
|
eth_data_inout(15 downto 0) => DM9000A_eth_data_inout(15 downto 0),
|
eth_data_inout(15 downto 0) => DM9000A_eth_data_inout(15 downto 0),
|
eth_interrupt_in => DM9000A_eth_interrupt_in,
|
eth_interrupt_in => DM9000A_eth_interrupt_in,
|
eth_read_out => DM9000A_eth_read_out,
|
eth_read_out => DM9000A_eth_read_out,
|
eth_reset_out => DM9000A_eth_reset_out,
|
eth_reset_out => DM9000A_eth_reset_out,
|
eth_write_out => DM9000A_eth_write_out,
|
eth_write_out => DM9000A_eth_write_out,
|
fatal_error_out => floodertx_udpfatal_error_out,
|
fatal_error_out => floodertx_udpfatal_error_out,
|
link_up_out => floodertx_udplink_up_out,
|
link_up_out => floodertx_udplink_up_out,
|
new_rx_out => udp_flooderrxnew_rx_out,
|
new_rx_out => udp_flooderrxnew_rx_out,
|
new_tx_in => floodertx_udpnew_tx_in,
|
new_tx_in => floodertx_udpnew_tx_in,
|
no_arp_target_MAC_in(47 downto 0) => floodertx_udpno_arp_target_MAC_in(47 downto 0),
|
no_arp_target_MAC_in(47 downto 0) => floodertx_udpno_arp_target_MAC_in(47 downto 0),
|
rst_n => rst_n_RESETn,
|
rst_n => rst_n_RESETn,
|
rx_data_out(15 downto 0) => udp_flooderrxrx_data_out(15 downto 0),
|
rx_data_out(15 downto 0) => udp_flooderrxrx_data_out(15 downto 0),
|
rx_data_valid_out => udp_flooderrxrx_data_valid_out,
|
rx_data_valid_out => udp_flooderrxrx_data_valid_out,
|
rx_erroneous_out => udp_flooderrxrx_erroneous_out,
|
rx_erroneous_out => udp_flooderrxrx_erroneous_out,
|
rx_error_out => udp_flooderrxrx_error_out,
|
rx_error_out => udp_flooderrxrx_error_out,
|
rx_len_out(10 downto 0) => udp_flooderrxrx_len_out(10 downto 0),
|
rx_len_out(10 downto 0) => udp_flooderrxrx_len_out(10 downto 0),
|
rx_re_in => udp_flooderrxrx_re_in,
|
rx_re_in => udp_flooderrxrx_re_in,
|
source_addr_out(31 downto 0) => udp_flooderrxsource_addr_out(31 downto 0),
|
source_addr_out(31 downto 0) => udp_flooderrxsource_addr_out(31 downto 0),
|
source_port_in(15 downto 0) => floodertx_udpsource_port_in(15 downto 0),
|
source_port_in(15 downto 0) => floodertx_udpsource_port_in(15 downto 0),
|
source_port_out(15 downto 0) => udp_flooderrxsource_port_out(15 downto 0),
|
source_port_out(15 downto 0) => udp_flooderrxsource_port_out(15 downto 0),
|
target_addr_in(31 downto 0) => floodertx_udptarget_addr_in(31 downto 0),
|
target_addr_in(31 downto 0) => floodertx_udptarget_addr_in(31 downto 0),
|
target_port_in(15 downto 0) => floodertx_udptarget_port_in(15 downto 0),
|
target_port_in(15 downto 0) => floodertx_udptarget_port_in(15 downto 0),
|
tx_data_in(15 downto 0) => floodertx_udptx_data_in(15 downto 0),
|
tx_data_in(15 downto 0) => floodertx_udptx_data_in(15 downto 0),
|
tx_data_valid_in => floodertx_udptx_data_valid_in,
|
tx_data_valid_in => floodertx_udptx_data_valid_in,
|
tx_len_in(10 downto 0) => floodertx_udptx_len_in(10 downto 0),
|
tx_len_in(10 downto 0) => floodertx_udptx_len_in(10 downto 0),
|
tx_re_out => floodertx_udptx_re_out
|
tx_re_out => floodertx_udptx_re_out
|
);
|
);
|
|
|
end kactusHierarchical;
|
end kactusHierarchical;
|
|
|
|
|
