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-- G.729A Codec self-test module synthesis script
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-- G.729A Codec self-test module synthesis script
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Tcl script g729a_selftest_syn.tcl creates a Quartus II project
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Tcl script g729a_selftest_syn.tcl creates a Quartus II project
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synthesizing G.729A codec self-test module and mapping it to
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synthesizing G.729A codec self-test module and mapping it to
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the Cyclone III FPGA on the NEEK development board.
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the Cyclone III FPGA on the NEEK development board.
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The script has been generated and tested using Quartus II ver.
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The script has been generated and tested using Quartus II ver.
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9.1.
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9.1.
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If the self-test module is succesfully synthesized, after
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If the self-test module is succesfully synthesized, after
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donwloading the resulting SOF file to the NEEK board, the board
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donwloading the resulting SOF file to the NEEK board, the board
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LED's should be in the following state:
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LED's should be in the following state:
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LED0 : on (test completed).
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LED1 : on (test completed).
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LED1 : on (test passed, no error).
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LED2 : on (test passed, no error).
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LED2 : off (permanently tied to VCC, just a safety check).
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LED3 : off (permanently tied to VCC, just a safety check).
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LED3 : on (permanently tied to GND, just a safety check).
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LED4 : on (permanently tied to GND, just a safety check).
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This directory includes all the design files required by the
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This directory includes all the design files required by the
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project:
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project:
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1) g729a_selftest_syn.tcl, tcl script creating self-test
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1) g729a_selftest_syn.tcl, tcl script creating self-test
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module project. This script uses relative path "..\..\VHDL"
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module project. This script uses relative path "..\..\VHDL"
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(pointing to VHDL directory in this release) to access source
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(pointing to VHDL directory in this release) to access source
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files: modify this path if files are located elsewhere.
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files: modify this path if files are located elsewhere.
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2) G729A_asip_romd.mif, G729A_asip_romd.mif,
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2) G729A_asip_romd.mif, G729A_asip_romd.mif,
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G729A_codec_sti_rom.mif and G729A_codec_sto_rom.mif, these are
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G729A_codec_sti_rom.mif and G729A_codec_sto_rom.mif, these are
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memory initialization files (written in Altera MIF format)
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memory initialization files (written in Altera MIF format)
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specifying data content for the various ROMs needed by the
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specifying data content for the various ROMs needed by the
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self-test module. These files must reside in the project
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self-test module. These files must reside in the project
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directory for Quartus to find them.
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directory for Quartus to find them.
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3) G729A_codec_selftest.vhd, this file is a copy of the file
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3) G729A_codec_selftest.vhd, this file is a copy of the file
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carrying the same name held in the VHDL directory, but with
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carrying the same name held in the VHDL directory, but with
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constant USE_ROM_MIF set to '1' in order to use ROM models
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constant USE_ROM_MIF set to '1' in order to use ROM models
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suitable for synthesis with Altera tools (e.g. using the MIF
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suitable for synthesis with Altera tools (e.g. using the MIF
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files of above).
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files of above).
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4) g729a_syn.bdf, schematic file instantiating self-test module
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4) g729a_syn.bdf, schematic file instantiating self-test module
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and some inverter (required to change polarity to reset signal
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and some inverter (required to change polarity to reset signal
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and to signals driving LEDs on NEEK board). This schematic is
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and to signals driving LEDs on NEEK board). This schematic is
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the project top-level module.
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the project top-level module.
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5) ext_clk.sdc, timing constraint file specifying input clock
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5) ext_clk.sdc, timing constraint file specifying input clock
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parameters (for a matter of simplicity, self-test module is
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parameters (for a matter of simplicity, self-test module is
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directly connected to board oscillator 50MHz clock).
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directly connected to board oscillator 50MHz clock).
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