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README for the SNESpad core
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README for the SNESpad core
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===========================
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===========================
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Version: $Date: 2004-10-06 16:42:15 $
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Version: $Date: 2004-10-06 16:42:15 $
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Description
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Description
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-----------
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The SNESpad core manages one or more gamepads of the Super Nintendo
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The SNESpad core manages one or more gamepads of the Super Nintendo
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Entertainment System in parallel. The button information is provided
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Entertainment System in parallel. The button information is provided
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statically at a simple interface with dedicated signal lines.
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statically at a simple interface with dedicated signal lines.
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The core has to be configured to fit into the integrating system. Details
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The core has to be configured to fit into the integrating system. Details
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about this are given in the section "Integration" below.
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about this are given in the section "Integration" below.
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Integration
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Integration
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-----------
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The interface of the SNESpad core is straight forward. It requires:
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The interface of the SNESpad core is straight forward. It requires:
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* a clock signal which is evaluated on the rising edge by the internal
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* a clock signal which is evaluated on the rising edge by the internal
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registers an asynchronous reset (active level is configurable)
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registers an asynchronous reset (active level is configurable)
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* connections to the gamepad(s)
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* connections to the gamepad(s)
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The button outputs should be self-describing.
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The button outputs should be self-describing.
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Configuration of the core is done via generics in the instantiation. There are
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Configuration of the core is done via generics in the instantiation. There are
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four generic parameters:
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four generic parameters:
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* num_pads_g - Number of pads connected to this controller instance (1 to n)
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* num_pads_g - Number of pads connected to this controller instance (1 to n)
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* reset_level_g - Active level of the asynchronous reset at port reset_i
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* reset_level_g - Active level of the asynchronous reset at port reset_i
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(0 = low active, 1 = high active)
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(0 = low active, 1 = high active)
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* button_level_g - Active level of the button outputs
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* button_level_g - Active level of the button outputs
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(0 = low active, 1 = high active)
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(0 = low active, 1 = high active)
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* clocks_per_6us_g - Number of clk_i cycles that elapse during 6 us (2 to x)
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* clocks_per_6us_g - Number of clk_i cycles that elapse during 6 us (2 to x)
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Button outputs and pad data input are arrays of num_pads_g width. The
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Button outputs and pad data input are arrays of num_pads_g width. The
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assignment is 1:1. i.e. the pad connected to pad_data_i(i) will propagate its
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assignment is 1:1. i.e. the pad connected to pad_data_i(i) will propagate its
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button status to but_a_o(i), but_b_o(i) etc. where i ranges from 0 to n-1.
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button status to but_a_o(i), but_b_o(i) etc. where i ranges from 0 to n-1.
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The communication to the SNES gamepad relies on a timebase of approximately
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The communication to the SNES gamepad relies on a timebase of approximately
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6 us. It is therefore necessary to adjust the counters inside the core via the
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6 us. It is therefore necessary to adjust the counters inside the core via the
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clock_per_6us_g generic parameter. Let's assume an example where the system
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clock_per_6us_g generic parameter. Let's assume an example where the system
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clock is running at 20 MHz. There are 20 clock cycles during 1 us, so the
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clock is running at 20 MHz. There are 20 clock cycles during 1 us, so the
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generic has to be set to 6 x 20 = 120.
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generic has to be set to 6 x 20 = 120.
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Adapter Hardware
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Adapter Hardware
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----------------
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----------------
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The required hardware setup is pretty simple if you reuse the connector of a
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The required hardware setup is pretty simple if you reuse the connector of a
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SNES console. It is quite robust and offers all connections centrally on the
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SNES console. It is quite robust and offers all connections centrally on the
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bottom side of the PCB at the pins for the cable socket. In addition, you will
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bottom side of the PCB at the pins for the cable socket. In addition, you will
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need an external 5V power source. Such a configuration is shown in the
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need an external 5V power source. Such a configuration is shown in the
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following picture.
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following picture.
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Pin B1 is the common Data Latch signal for Pad 1 and Pad 2. The pins B2 and T2
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Pin B1 is the common Data Latch signal for Pad 1 and Pad 2. The pins B2 and T2
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are the Data Clock for Pad 1 and Pad 2, respectively. They have to be
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are the Data Clock for Pad 1 and Pad 2, respectively. They have to be
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connected together to pad_clock_i as the core clocks both pads
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connected together to pad_clock_i as the core clocks both pads
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simultaneously. Pin B3 is the Serial Data of Pad 1 and Pin B4 is the Serial
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simultaneously. Pin B3 is the Serial Data of Pad 1 and Pin B4 is the Serial
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Data of Pad 2. Each data line requires a 10 kOhm pull-up resistor.
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Data of Pad 2. Each data line requires a 10 kOhm pull-up resistor.
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See snespad.png
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See snespad.png
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Verification
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Verification
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------------
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The SNESpad core comes with a simple testbench that simulates two SNES
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The SNESpad core comes with a simple testbench that simulates two SNES
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gamepads. Serial information is sent to the core and the reported button
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gamepads. Serial information is sent to the core and the reported button
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states are compared against the input.
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states are compared against the input.
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You should normally not need to run the testbench. But in case you modified
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You should normally not need to run the testbench. But in case you modified
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the VHDL code the testbench gives some hints if the design has been broken.
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the VHDL code the testbench gives some hints if the design has been broken.
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Directory Structure
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Directory Structure
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-------------------
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The core's directory structure follows the proposal of OpenCores.org.
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The core's directory structure follows the proposal of OpenCores.org.
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snespad
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snespad
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\--+-- rtl
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\--+-- rtl
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| \-- vhdl : VHDL code containing the RTL description
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| \-- vhdl : VHDL code containing the RTL description
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| of the core.
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| of the core.
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+-- bench
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+-- bench
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| \-- vhdl : VHDL testbench code.
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| \-- vhdl : VHDL testbench code.
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\-- sim
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\-- sim
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\-- rtl_sim : Directory for running simulations.
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\-- rtl_sim : Directory for running simulations.
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Compiling the VHDL Code
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Compiling the VHDL Code
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-----------------------
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-----------------------
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VHDL compilation and simulation tasks take place inside in sim/rtl_sim
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VHDL compilation and simulation tasks take place inside in sim/rtl_sim
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directory. The project setup supports only the GHDL simulator (see
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directory. The project setup supports only the GHDL simulator (see
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http://ghdl.free.fr).
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http://ghdl.free.fr).
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To compile the code simply type at the shell
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To compile the code simply type at the shell
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$ make
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$ make
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This should result in a file called tb_behav_c0 which can be executed as any
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This should result in a file called tb_behav_c0 which can be executed as any
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other executable.
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other executable.
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The basic simple sequence list can be found in COMPILE_LIST. This can be
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The basic simple sequence list can be found in COMPILE_LIST. This can be
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useful to quickly set up the analyze stage of any compiler or
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useful to quickly set up the analyze stage of any compiler or
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synthesizer. Especially when synthesizing the code, you want to skip the VHDL
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synthesizer. Especially when synthesizing the code, you want to skip the VHDL
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configurations in *-c.vhd and everything below the bench/ directory.
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configurations in *-c.vhd and everything below the bench/ directory.
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References
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References
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* Gamepads project at OpenCores.org
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* Gamepads project at OpenCores.org
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http://www.opencores.org/projects.cgi/web/gamepads/overview
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http://www.opencores.org/projects.cgi/web/gamepads/overview
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* The Hardware Book
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* The Hardware Book
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http://www.hardwarebook.net/connector/userinput/snescontroller.html
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http://www.hardwarebook.net/connector/userinput/snescontroller.html
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* Linux gamecon driver
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* Linux gamecon driver
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http://lxr.linux.no/source/drivers/char/joystick/gamecon.c?v=2.4.26
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http://lxr.linux.no/source/drivers/char/joystick/gamecon.c?v=2.4.26
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