/* GECKO3COM
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/* GECKO3COM
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*
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*
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* Copyright (C) 2008 by
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* Copyright (C) 2008 by
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* ___ ____ _ _
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* ___ ____ _ _
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* ( _`\ ( __)( ) ( )
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* ( _`\ ( __)( ) ( )
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* | (_) )| (_ | |_| | Bern University of Applied Sciences
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* | (_) )| (_ | |_| | Bern University of Applied Sciences
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* | _ <'| _) | _ | School of Engineering and
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* | _ <'| _) | _ | School of Engineering and
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* | (_) )| | | | | | Information Technology
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* | (_) )| | | | | | Information Technology
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* (____/'(_) (_) (_)
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* (____/'(_) (_) (_)
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*
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*
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* (at your option) any later version.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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/*********************************************************************/
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/*********************************************************************/
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/** \file fpga_load.c
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/** \file fpga_load.c
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*********************************************************************
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*********************************************************************
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* \brief functions to programm an FPGA
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* \brief functions to programm an FPGA
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*
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*
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* These functions handle the bit file for an Xilinx Spartan3
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* These functions handle the bit file for an Xilinx Spartan3
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* FPGA and programm it in parallel slave mode.
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* FPGA and programm it in parallel slave mode.
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*
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*
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* \note Currently only Xilinx FPGA's are supported, function stubs
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* \note Currently only Xilinx FPGA's are supported, function stubs
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* to handle Altera are provided as a guide for porting.
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* to handle Altera are provided as a guide for porting.
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*
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*
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* \author GNUradio team, Matthias Zurbrügg bfh.ch,
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* \author GNUradio team, Matthias Zurbrügg bfh.ch,
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* Christoph Zimmermann bfh.ch
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* Christoph Zimmermann bfh.ch
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* \date 2009-1-13
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* \date 2009-1-13
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*
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*
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*/
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*/
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#include "gecko3com_common.h"
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#include "gecko3com_common.h"
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#include "gecko3com_regs.h"
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#include "gecko3com_regs.h"
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#include "fpga_load.h"
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#include "fpga_load.h"
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#include "delay.h"
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#include "delay.h"
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#include "debugprint.h"
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#include "debugprint.h"
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/* Xilinx stuff. We use slave parallel mode (select map) to configure the FPGA
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/* Xilinx stuff. We use slave parallel mode (select map) to configure the FPGA
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*/
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*/
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#ifdef XILINX
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#ifdef XILINX
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/** makro to toggle the configuration clock line */
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/** makro to toggle the configuration clock line */
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#define toggle_cclk() { \
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#define toggle_cclk() { \
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XILINX_CCLK &= ~bmXILINX_CCLK; /* bring CCLK low */ \
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XILINX_CCLK &= ~bmXILINX_CCLK; /* bring CCLK low */ \
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XILINX_CCLK |= bmXILINX_CCLK; /* bring CCLK high */ \
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XILINX_CCLK |= bmXILINX_CCLK; /* bring CCLK high */ \
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}
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}
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void init_fpga_interface(void) {
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void init_fpga_interface(void) {
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/* IFCLK is generated internally and runs at 48 MHz; IO Pins configured as normal Ports */
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/* IFCLK is generated internally and runs at 48 MHz; IO Pins configured as normal Ports */
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//IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;
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//IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;
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IFCONFIG = bmIFCLKSRC | bmIFCLKOE;
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IFCONFIG = bmIFCLKSRC | bmIFCLKOE;
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SYNCDELAY;
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SYNCDELAY;
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}
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}
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int8_t fpga_scan_file(const xdata unsigned char *p, idata uint16_t *offset, \
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int8_t fpga_scan_file(const xdata unsigned char *p, idata uint16_t *offset, \
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idata uint16_t *length, xdata Fpga_Info* info)
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idata uint16_t *length, xdata Fpga_Info* info)
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{
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{
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idata uint8_t string_length = 0, chars_left_to_read = 0;
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idata uint8_t string_length = 0, chars_left_to_read = 0;
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xdata uint16_t local_position = *offset;
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xdata uint16_t local_position = *offset;
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for(local_position; local_position < *length; local_position++) {
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for(local_position; local_position < *length; local_position++) {
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//printf_tiny("fi: %d\n",local_position);
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//printf_tiny("fi: %d\n",local_position);
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/* information found, copy data to output array */
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/* information found, copy data to output array */
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if(chars_left_to_read < string_length) {
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if(chars_left_to_read < string_length) {
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info->info[chars_left_to_read++] = p[local_position];
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info->info[chars_left_to_read++] = p[local_position];
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/* end of information, return successfull */
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/* end of information, return successfull */
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if(chars_left_to_read == string_length) {
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if(chars_left_to_read == string_length) {
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info->position = local_position;
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info->position = local_position;
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*offset = local_position+1;
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*offset = local_position+1;
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return FPGA_INFO_COMPLETE;
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return FPGA_INFO_COMPLETE;
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}
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}
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else {
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else {
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continue; /* ignore rest of these loop, load next character */
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continue; /* ignore rest of these loop, load next character */
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}
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}
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}
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}
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/* search for the start of the desired type of information */
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/* search for the start of the desired type of information */
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if(chars_left_to_read == 0 && p[local_position] == info->type){
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if(chars_left_to_read == 0 && p[local_position] == info->type){
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chars_left_to_read = 1;
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chars_left_to_read = 1;
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continue; /* ignore rest of these loop, load next character */
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continue; /* ignore rest of these loop, load next character */
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}
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}
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/* start character found, check next character if it is \0 */
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/* start character found, check next character if it is \0 */
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if(chars_left_to_read == 1) {
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if(chars_left_to_read == 1) {
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if(p[local_position] == 0) {
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if(p[local_position] == 0) {
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chars_left_to_read = 2;
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chars_left_to_read = 2;
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}
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}
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else {
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else {
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/* false alert, continue searching */
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/* false alert, continue searching */
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chars_left_to_read = 0;
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chars_left_to_read = 0;
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}
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}
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continue; /* ignore rest of these loop, load next character */
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continue; /* ignore rest of these loop, load next character */
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}
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}
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/* start of information found, copy length of following string */
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/* start of information found, copy length of following string */
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if(chars_left_to_read == 2) {
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if(chars_left_to_read == 2) {
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chars_left_to_read = 0;
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chars_left_to_read = 0;
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if(p[local_position] > FPGA_INFO_LEN) {
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if(p[local_position] > FPGA_INFO_LEN) {
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string_length = FPGA_INFO_LEN;
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string_length = FPGA_INFO_LEN;
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}
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}
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else {
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else {
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string_length = p[local_position];
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string_length = p[local_position];
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}
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}
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/* exception: file length has a fixed length */
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/* exception: file length has a fixed length */
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if(info->type == FILE_LENGTH) {
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if(info->type == FILE_LENGTH) {
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string_length = 3;
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string_length = 3;
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chars_left_to_read = 1;
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chars_left_to_read = 1;
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info->info[0] = p[local_position];
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info->info[0] = p[local_position];
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}
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}
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}
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}
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/* end of for loop. nothing found yet, load next character */
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/* end of for loop. nothing found yet, load next character */
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}
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}
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/* end of packet reached, no info found or not finished copying string */
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/* end of packet reached, no info found or not finished copying string */
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info->position = local_position;
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info->position = local_position;
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*offset = local_position;
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*offset = local_position;
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return FPGA_INFO_NOT_COMPLETE;
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return FPGA_INFO_NOT_COMPLETE;
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}
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}
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uint8_t fpga_load_begin(void)
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uint8_t fpga_load_begin(void)
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{
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{
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idata uint8_t i;
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idata uint8_t i;
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/* enable autopointer 0 */
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/* enable autopointer 0 */
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AUTOPTRSETUP = bmAPTREN | bmAPTR1INC;
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AUTOPTRSETUP = bmAPTREN | bmAPTR1INC;
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/* CS_B, RDWR_B should be high after board initialization
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/* CS_B, RDWR_B should be high after board initialization
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* but when something went wrong during fpga config the state is unknown */
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* but when something went wrong during fpga config the state is unknown */
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if(!(XILINX_CS_B | bmXILINX_CS_B) || !(XILINX_RDWR_B | bmXILINX_RDWR_B)) {
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if(!(XILINX_CS_B | bmXILINX_CS_B) || !(XILINX_RDWR_B | bmXILINX_RDWR_B)) {
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/* bring first RDWR_B high to signal ABORT to the FPGA */
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/* bring first RDWR_B high to signal ABORT to the FPGA */
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XILINX_RDWR_B |= bmXILINX_RDWR_B;
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XILINX_RDWR_B |= bmXILINX_RDWR_B;
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/* toggle CCLK four times more to complete the abort sequenze */
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/* toggle CCLK four times more to complete the abort sequenze */
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for(i=0; i<4; i++) {
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for(i=0; i<4; i++) {
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toggle_cclk();
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toggle_cclk();
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}
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}
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XILINX_CS_B |= bmXILINX_CS_B;
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XILINX_CS_B |= bmXILINX_CS_B;
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}
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}
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/* bring Prog_B low brings the device in the initalisation mode */
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/* bring Prog_B low brings the device in the initalisation mode */
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XILINX_PROG_B &= ~bmXILINX_PROG_B;
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XILINX_PROG_B &= ~bmXILINX_PROG_B;
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udelay(100); // and hold it there
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udelay(100); // and hold it there
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/* bring Prog_B bit high */
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/* bring Prog_B bit high */
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XILINX_PROG_B |= bmXILINX_PROG_B;
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XILINX_PROG_B |= bmXILINX_PROG_B;
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/* if Init_B goes high the device is in the configuration load mode */
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/* if Init_B goes high the device is in the configuration load mode */
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for(i=0;i<50;i++) {
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for(i=0;i<50;i++) {
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if(XILINX_INIT_B & bmXILINX_INIT_B) {
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if(XILINX_INIT_B & bmXILINX_INIT_B) {
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//if(1) { /* this line is needed for LA tests, uncomment this and comment the line befor */
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//if(1) { /* this line is needed for LA tests, uncomment this and comment the line befor */
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/* bring CS_B, RDWR_B low */
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/* bring CS_B, RDWR_B low */
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XILINX_RDWR_B &= ~bmXILINX_RDWR_B;
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XILINX_RDWR_B &= ~bmXILINX_RDWR_B;
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XILINX_CS_B &= ~bmXILINX_CS_B;
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XILINX_CS_B &= ~bmXILINX_CS_B;
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return 1;
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return 1;
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}
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}
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mdelay(1);
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mdelay(1);
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}
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}
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/* FPGA not ready to configure */
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/* FPGA not ready to configure */
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return 0;
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return 0;
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}
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}
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uint8_t fpga_load_xfer(xdata unsigned char *p, idata uint16_t *offset, \
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uint8_t fpga_load_xfer(xdata unsigned char *p, idata uint16_t *offset, \
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idata uint16_t *bytecount)
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idata uint16_t *bytecount)
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{
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{
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idata uint16_t local_count;
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idata uint16_t local_count;
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uint8_t local_data;
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uint8_t local_data;
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//printf_tiny("off %d ",local_count);
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//printf_tiny("off %d ",local_count);
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//printf_tiny("c %d\n",*bytecount);
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//printf_tiny("c %d\n",*bytecount);
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local_count = *offset;
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local_count = *offset;
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/* setup autopointer source adress from parameter p and the offset */
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/* setup autopointer source adress from parameter p and the offset */
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AUTOPTRH1 = ((uintptr_t)p >> 8);
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AUTOPTRH1 = ((uintptr_t)p >> 8);
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AUTOPTRL1 = ((uintptr_t)p & 0xFF);
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AUTOPTRL1 = ((uintptr_t)p & 0xFF);
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AUTOPTRH1 += (local_count >> 8);
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AUTOPTRH1 += (local_count >> 8);
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AUTOPTRL1 += (local_count & 0xFF);
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AUTOPTRL1 += (local_count & 0xFF);
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/* setup a for loop to send the data to the fpga data port */
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/* setup a for loop to send the data to the fpga data port */
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for(local_count; local_count < *bytecount; local_count++ ) {
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for(local_count; local_count < *bytecount; local_count++ ) {
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//XILINX_DATA = AUTODAT1; // drive Data Port with data
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//XILINX_DATA = AUTODAT1; // drive Data Port with data
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local_data = AUTODAT1;
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local_data = AUTODAT1;
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XILINX_DATA = local_data;
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XILINX_DATA = local_data;
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|
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toggle_cclk();
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toggle_cclk();
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|
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//printf_tiny("0x%x ",local_data);
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//printf_tiny("0x%x ",local_data);
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|
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/* no need for us because we are way to slow that a busy occours */
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/* no need for us because we are way to slow that a busy occours */
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/* loop while busy is true */
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/* loop while busy is true */
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/*while((XILINX_BUSY & bmXILINX_BUSY) == bmXILINX_BUSY) {
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/*while((XILINX_BUSY & bmXILINX_BUSY) == bmXILINX_BUSY) {
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// if FPGA busy, toggle CCLK
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// if FPGA busy, toggle CCLK
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toggle_cclk();
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toggle_cclk();
|
}
|
}
|
*/
|
*/
|
}
|
}
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|
|
*offset += *bytecount;
|
*offset += *bytecount;
|
return 1;
|
return 1;
|
}
|
}
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|
|
|
|
/*
|
/*
|
* check for successful load...
|
* check for successful load...
|
*/
|
*/
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uint8_t
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uint8_t
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fpga_load_end(void)
|
fpga_load_end(void)
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{
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{
|
idata uint8_t i;
|
idata uint8_t i;
|
|
|
/* toggle CCLK four times more to complete the startup sequenze */
|
/* toggle CCLK four times more to complete the startup sequenze */
|
for(i=0; i<4; i++) {
|
for(i=0; i<4; i++) {
|
toggle_cclk();
|
toggle_cclk();
|
}
|
}
|
|
|
/* bring CS_B, RDWR_B high */
|
/* bring CS_B, RDWR_B high */
|
XILINX_CS_B |= bmXILINX_CS_B;
|
XILINX_CS_B |= bmXILINX_CS_B;
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XILINX_RDWR_B |= bmXILINX_RDWR_B;
|
XILINX_RDWR_B |= bmXILINX_RDWR_B;
|
|
|
if(!fpga_done()) {
|
if(!fpga_done()) {
|
/* if not DONE, an error occoured during configuration */
|
/* if not DONE, an error occoured during configuration */
|
print_err("fin.\n");
|
//print_err("fin.\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
#endif /* XILINX */
|
#endif /* XILINX */
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
/* Altera stuff. only copied from USRP source code. does not work. only a
|
/* Altera stuff. only copied from USRP source code. does not work. only a
|
* guide to give you a start to port GECKO3COM to other boards using Altera
|
* guide to give you a start to port GECKO3COM to other boards using Altera
|
* devices
|
* devices
|
*/
|
*/
|
|
|
#ifdef ALTERA
|
#ifdef ALTERA
|
/*
|
/*
|
* setup altera FPGA serial load (PS).
|
* setup altera FPGA serial load (PS).
|
*
|
*
|
* On entry:
|
* On entry:
|
* don't care
|
* don't care
|
*
|
*
|
* On exit:
|
* On exit:
|
* ALTERA_DCLK = 0
|
* ALTERA_DCLK = 0
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NSTATUS = 1 (input)
|
* ALTERA_NSTATUS = 1 (input)
|
*/
|
*/
|
uint8_t
|
uint8_t
|
fpga_load_begin(void)
|
fpga_load_begin(void)
|
{
|
{
|
ALTERA_CONFIG &= ~bmALTERA_BITS; // clear all bits (NCONFIG low)
|
ALTERA_CONFIG &= ~bmALTERA_BITS; // clear all bits (NCONFIG low)
|
udelay (40); // wait 40 us
|
udelay (40); // wait 40 us
|
ALTERA_CONFIG |= bmALTERA_NCONFIG; // set NCONFIG high
|
ALTERA_CONFIG |= bmALTERA_NCONFIG; // set NCONFIG high
|
|
|
if (UC_BOARD_HAS_FPGA){
|
if (UC_BOARD_HAS_FPGA){
|
// FIXME should really cap this loop with a counter so we
|
// FIXME should really cap this loop with a counter so we
|
// don't hang forever on a hardware failure.
|
// don't hang forever on a hardware failure.
|
while ((USRP_ALTERA_CONFIG & bmALTERA_NSTATUS) == 0) // wait for NSTATUS to go high
|
while ((USRP_ALTERA_CONFIG & bmALTERA_NSTATUS) == 0) // wait for NSTATUS to go high
|
;
|
;
|
}
|
}
|
|
|
// ready to xfer now
|
// ready to xfer now
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/*
|
/*
|
* clock out the low bit of bits.
|
* clock out the low bit of bits.
|
*
|
*
|
* On entry:
|
* On entry:
|
* ALTERA_DCLK = 0
|
* ALTERA_DCLK = 0
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NSTATUS = 1 (input)
|
* ALTERA_NSTATUS = 1 (input)
|
*
|
*
|
* On exit:
|
* On exit:
|
* ALTERA_DCLK = 0
|
* ALTERA_DCLK = 0
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NSTATUS = 1 (input)
|
* ALTERA_NSTATUS = 1 (input)
|
*/
|
*/
|
|
|
static void
|
static void
|
clock_out_config_byte(const uint8_t bits) _naked
|
clock_out_config_byte(const uint8_t bits) _naked
|
{
|
{
|
_asm
|
_asm
|
mov a, dpl
|
mov a, dpl
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
rrc a
|
rrc a
|
mov _bitALTERA_DATA0,c
|
mov _bitALTERA_DATA0,c
|
setb _bitALTERA_DCLK
|
setb _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
clr _bitALTERA_DCLK
|
|
|
ret
|
ret
|
|
|
_endasm;
|
_endasm;
|
}
|
}
|
|
|
static void
|
static void
|
clock_out_bytes(const uint8_t bytecount,
|
clock_out_bytes(const uint8_t bytecount,
|
uint8_t xdata *p)
|
uint8_t xdata *p)
|
{
|
{
|
while (bytecount-- > 0)
|
while (bytecount-- > 0)
|
clock_out_config_byte (*p++);
|
clock_out_config_byte (*p++);
|
}
|
}
|
|
|
/*
|
/*
|
* Transfer block of bytes from packet to FPGA serial configuration port
|
* Transfer block of bytes from packet to FPGA serial configuration port
|
*
|
*
|
* On entry:
|
* On entry:
|
* ALTERA_DCLK = 0
|
* ALTERA_DCLK = 0
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NSTATUS = 1 (input)
|
* ALTERA_NSTATUS = 1 (input)
|
*
|
*
|
* On exit:
|
* On exit:
|
* ALTERA_DCLK = 0
|
* ALTERA_DCLK = 0
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NCONFIG = 1
|
* ALTERA_NSTATUS = 1 (input)
|
* ALTERA_NSTATUS = 1 (input)
|
*/
|
*/
|
uint8_t
|
uint8_t
|
fpga_load_xfer(const xdata uint8_t *p, const uint8_t bytecount)
|
fpga_load_xfer(const xdata uint8_t *p, const uint8_t bytecount)
|
{
|
{
|
clock_out_bytes (bytecount, p);
|
clock_out_bytes (bytecount, p);
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/*
|
/*
|
* check for successful load...
|
* check for successful load...
|
*/
|
*/
|
uint8_t
|
uint8_t
|
fpga_load_end(void)
|
fpga_load_end(void)
|
{
|
{
|
uint8_t status = ALTERA_CONFIG;
|
uint8_t status = ALTERA_CONFIG;
|
|
|
if (!UC_BOARD_HAS_FPGA) // always true if we don't have FPGA
|
if (!UC_BOARD_HAS_FPGA) // always true if we don't have FPGA
|
return 1;
|
return 1;
|
|
|
if ((status & bmALTERA_NSTATUS) == 0) // failed to program
|
if ((status & bmALTERA_NSTATUS) == 0) // failed to program
|
return 0;
|
return 0;
|
|
|
if ((status & bmALTERA_CONF_DONE) == bmALTERA_CONF_DONE)
|
if ((status & bmALTERA_CONF_DONE) == bmALTERA_CONF_DONE)
|
return 1; // everything's cool
|
return 1; // everything's cool
|
|
|
// I don't think this should happen. It indicates that
|
// I don't think this should happen. It indicates that
|
// programming is still in progress.
|
// programming is still in progress.
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
#endif /* ALTERA */
|
#endif /* ALTERA */
|
|
|
