-- GECKO3COM IP Core
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-- GECKO3COM IP Core
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--
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--
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-- Copyright (C) 2009 by
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-- Copyright (C) 2009 by
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-- ___ ___ _ _
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-- ___ ___ _ _
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-- ( _ \ ( __)( ) ( )
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-- ( _ \ ( __)( ) ( )
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | _ < | _) | _ | School of Engineering and
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-- | _ < | _) | _ | School of Engineering and
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-- | (_) )| | | | | | Information Technology
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-- | (_) )| | | | | | Information Technology
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-- (____/ (_) (_) (_)
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-- (____/ (_) (_) (_)
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- URL to the project description:
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-- URL to the project description:
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Author: Christoph Zimmermann
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-- Author: Christoph Zimmermann
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-- Date of creation: 16:52:52 01/28/2010
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-- Date of creation: 16:52:52 01/28/2010
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-- Description:
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-- Description:
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-- This is the top module for the GECKO3com simple IP core.
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-- This is the top module for the GECKO3com simple IP core.
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-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
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-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
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--
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--
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-- This core provides a simple FIFO and register interface to the
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-- This core provides a simple FIFO and register interface to the
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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--
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--
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-- Look at GECKO3COM_simple.vhd for an example how to use it.
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-- Look at GECKO3COM_simple.vhd for an example how to use it.
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--
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--
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-- Target Devices: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
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-- Target Devices: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
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-- Tool versions: 11.1
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-- Tool versions: 11.1
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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library work;
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use work.GECKO3COM_defines.all;
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use work.GECKO3COM_defines.all;
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entity GECKO3COM_simple is
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entity GECKO3COM_simple is
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generic (
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generic (
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BUSWIDTH : integer := 16); -- vector size of the FIFO databusses
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BUSWIDTH : integer := 16); -- vector size of the FIFO databusses
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_sysclk : in std_logic; -- FPGA System CLK
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i_sysclk : in std_logic; -- FPGA System CLK
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i_receive_fifo_rd_en : in std_logic;
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i_receive_fifo_rd_en : in std_logic;
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o_receive_fifo_empty : out std_logic;
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o_receive_fifo_empty : out std_logic;
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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o_receive_end_of_message : out std_logic;
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o_receive_end_of_message : out std_logic;
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o_receive_newdata : out std_logic;
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o_receive_newdata : out std_logic;
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i_send_fifo_wr_en : in std_logic;
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i_send_fifo_wr_en : in std_logic;
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o_send_fifo_full : out std_logic;
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o_send_fifo_full : out std_logic;
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize_en : in std_logic;
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i_send_transfersize_en : in std_logic;
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i_send_have_more_data : in std_logic;
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i_send_have_more_data : in std_logic;
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o_send_data_request : out std_logic;
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o_send_data_request : out std_logic;
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o_send_finished : out std_logic;
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o_send_finished : out std_logic;
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o_rx : out std_logic; -- receiving data signalisation
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o_rx : out std_logic; -- receiving data signalisation
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o_tx : out std_logic; -- transmitting data signalisation
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o_tx : out std_logic; -- transmitting data signalisation
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-- Interface signals to the EZ-USB FX2
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-- Interface signals to the EZ-USB FX2
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
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i_WRU : in std_logic; -- write from GPIF
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i_WRU : in std_logic; -- write from GPIF
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i_RDYU : in std_logic; -- GPIF is ready
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i_RDYU : in std_logic; -- GPIF is ready
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o_WRX : out std_logic; -- To write to GPIF
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o_WRX : out std_logic; -- To write to GPIF
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o_RDYX : out std_logic; -- IP Core is ready
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o_RDYX : out std_logic; -- IP Core is ready
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b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0) -- bidirect data bus
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b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0) -- bidirect data bus
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);
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);
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end GECKO3COM_simple;
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end GECKO3COM_simple;
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architecture Behavioral of GECKO3COM_simple is
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architecture Behavioral of GECKO3COM_simple is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- COMPONENTS
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-- COMPONENTS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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component gpif_com
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component gpif_com
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_SYSCLK : in std_logic;
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i_SYSCLK : in std_logic;
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o_ABORT : out std_logic;
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o_ABORT : out std_logic;
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o_RX : out std_logic;
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o_RX : out std_logic;
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o_TX : out std_logic;
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o_TX : out std_logic;
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i_RD_EN : in std_logic;
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i_RD_EN : in std_logic;
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o_EMPTY : out std_logic;
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o_EMPTY : out std_logic;
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o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_EOM : in std_logic;
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i_EOM : in std_logic;
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i_WR_EN : in std_logic;
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i_WR_EN : in std_logic;
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o_FULL : out std_logic;
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o_FULL : out std_logic;
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i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_IFCLK : in std_logic;
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i_IFCLK : in std_logic;
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i_WRU : in std_logic;
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i_WRU : in std_logic;
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i_RDYU : in std_logic;
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i_RDYU : in std_logic;
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o_WRX : out std_logic;
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o_WRX : out std_logic;
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o_RDYX : out std_logic;
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o_RDYX : out std_logic;
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b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));
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b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));
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end component;
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end component;
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component GECKO3COM_simple_datapath
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component GECKO3COM_simple_datapath
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generic (
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generic (
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BUSWIDTH : integer);
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BUSWIDTH : integer);
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_sysclk : in std_logic;
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i_sysclk : in std_logic;
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i_rx_data : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_rx_data : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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o_tx_data : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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o_tx_data : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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i_receive_fifo_rd_en : in std_logic;
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i_receive_fifo_rd_en : in std_logic;
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i_receive_fifo_wr_en : in std_logic;
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i_receive_fifo_wr_en : in std_logic;
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o_receive_fifo_empty : out std_logic;
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o_receive_fifo_empty : out std_logic;
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o_receive_fifo_full : out std_logic;
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o_receive_fifo_full : out std_logic;
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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i_receive_fifo_reset : in std_logic;
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i_receive_fifo_reset : in std_logic;
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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i_receive_counter_load : in std_logic;
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i_receive_counter_load : in std_logic;
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i_receive_counter_en : in std_logic;
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i_receive_counter_en : in std_logic;
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o_receive_counter_zero : out std_logic;
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o_receive_counter_zero : out std_logic;
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o_dev_dep_msg_out : out std_logic;
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o_dev_dep_msg_out : out std_logic;
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o_request_dev_dep_msg_in : out std_logic;
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o_request_dev_dep_msg_in : out std_logic;
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i_btag_reg_en : in std_logic;
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i_btag_reg_en : in std_logic;
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i_nbtag_reg_en : in std_logic;
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i_nbtag_reg_en : in std_logic;
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o_btag_correct : out std_logic;
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o_btag_correct : out std_logic;
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o_eom_bit_detected : out std_logic;
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o_eom_bit_detected : out std_logic;
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i_send_fifo_rd_en : in std_logic;
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i_send_fifo_rd_en : in std_logic;
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i_send_fifo_wr_en : in std_logic;
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i_send_fifo_wr_en : in std_logic;
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o_send_fifo_empty : out std_logic;
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o_send_fifo_empty : out std_logic;
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o_send_fifo_full : out std_logic;
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o_send_fifo_full : out std_logic;
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_fifo_reset : in std_logic;
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i_send_fifo_reset : in std_logic;
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize_en : in std_logic;
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i_send_transfersize_en : in std_logic;
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i_send_have_more_data : in std_logic;
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i_send_have_more_data : in std_logic;
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i_send_counter_load : in std_logic;
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i_send_counter_load : in std_logic;
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i_send_counter_en : in std_logic;
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i_send_counter_en : in std_logic;
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o_send_counter_zero : out std_logic;
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o_send_counter_zero : out std_logic;
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i_send_mux_sel : in std_logic_vector(2 downto 0);
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i_send_mux_sel : in std_logic_vector(2 downto 0);
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o_send_finished : out std_logic;
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i_receive_newdata_set : in std_logic;
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i_receive_newdata_set : in std_logic;
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o_receive_newdata : out std_logic;
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o_receive_newdata : out std_logic;
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i_receive_end_of_message_set : in std_logic;
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i_receive_end_of_message_set : in std_logic;
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o_receive_end_of_message : out std_logic;
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o_receive_end_of_message : out std_logic;
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i_send_data_request_set : in std_logic;
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i_send_data_request_set : in std_logic;
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o_send_data_request : out std_logic);
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o_send_data_request : out std_logic);
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end component;
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end component;
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component GECKO3COM_simple_fsm
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component GECKO3COM_simple_fsm
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_sysclk : in std_logic;
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i_sysclk : in std_logic;
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o_receive_fifo_wr_en : out std_logic;
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o_receive_fifo_wr_en : out std_logic;
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i_receive_fifo_full : in std_logic;
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i_receive_fifo_full : in std_logic;
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o_receive_fifo_reset : out std_logic;
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o_receive_fifo_reset : out std_logic;
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o_receive_transfersize_en : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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o_receive_transfersize_en : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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o_receive_counter_load : out std_logic;
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o_receive_counter_load : out std_logic;
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o_receive_counter_en : out std_logic;
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o_receive_counter_en : out std_logic;
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i_receive_counter_zero : in std_logic;
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i_receive_counter_zero : in std_logic;
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i_dev_dep_msg_out : in std_logic;
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i_dev_dep_msg_out : in std_logic;
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i_request_dev_dep_msg_in : in std_logic;
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i_request_dev_dep_msg_in : in std_logic;
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o_btag_reg_en : out std_logic;
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o_btag_reg_en : out std_logic;
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o_nbtag_reg_en : out std_logic;
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o_nbtag_reg_en : out std_logic;
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i_btag_correct : in std_logic;
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i_btag_correct : in std_logic;
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i_eom_bit_detected : in std_logic;
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i_eom_bit_detected : in std_logic;
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i_send_transfersize_en : in std_logic;
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i_send_transfersize_en : in std_logic;
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o_send_fifo_rd_en : out std_logic;
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o_send_fifo_rd_en : out std_logic;
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i_send_fifo_empty : in std_logic;
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i_send_fifo_empty : in std_logic;
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o_send_fifo_reset : out std_logic;
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o_send_fifo_reset : out std_logic;
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o_send_counter_load : out std_logic;
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o_send_counter_load : out std_logic;
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o_send_counter_en : out std_logic;
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o_send_counter_en : out std_logic;
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i_send_counter_zero : in std_logic;
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i_send_counter_zero : in std_logic;
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o_send_mux_sel : out std_logic_vector(2 downto 0);
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o_send_mux_sel : out std_logic_vector(2 downto 0);
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o_send_finished : out std_logic;
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o_receive_newdata_set : out std_logic;
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o_receive_newdata_set : out std_logic;
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o_receive_end_of_message_set : out std_logic;
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o_receive_end_of_message_set : out std_logic;
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o_send_data_request_set : out std_logic;
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o_send_data_request_set : out std_logic;
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i_gpif_rx : in std_logic;
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i_gpif_rx : in std_logic;
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i_gpif_rx_empty : in std_logic;
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i_gpif_rx_empty : in std_logic;
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o_gpif_rx_rd_en : out std_logic;
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o_gpif_rx_rd_en : out std_logic;
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i_gpif_tx : in std_logic;
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i_gpif_tx : in std_logic;
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i_gpif_tx_full : in std_logic;
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i_gpif_tx_full : in std_logic;
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o_gpif_tx_wr_en : out std_logic;
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o_gpif_tx_wr_en : out std_logic;
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i_gpif_abort : in std_logic;
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i_gpif_abort : in std_logic;
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o_gpif_eom : out std_logic);
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o_gpif_eom : out std_logic);
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end component;
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end component;
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|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- interconection signals
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-- interconection signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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|
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-- gpif_com internal signals
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-- gpif_com internal signals
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signal s_gpif_abort : std_logic;
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signal s_gpif_abort : std_logic;
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signal s_gpif_rx_rd_en : std_logic;
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signal s_gpif_rx_rd_en : std_logic;
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signal s_gpif_rx_empty : std_logic;
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signal s_gpif_rx_empty : std_logic;
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signal s_gpif_rx_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_gpif_rx_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_gpif_rx : std_logic;
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signal s_gpif_rx : std_logic;
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signal s_gpif_eom : std_logic;
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signal s_gpif_eom : std_logic;
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signal s_gpif_tx_wr_en : std_logic;
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signal s_gpif_tx_wr_en : std_logic;
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signal s_gpif_tx_full : std_logic;
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signal s_gpif_tx_full : std_logic;
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signal s_gpif_tx_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_gpif_tx_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_gpif_tx : std_logic;
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signal s_gpif_tx : std_logic;
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|
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-- GECKO3COM_simple_datapath internal signals
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-- GECKO3COM_simple_datapath internal signals
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signal s_receive_fifo_wr_en : std_logic;
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signal s_receive_fifo_wr_en : std_logic;
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signal s_receive_fifo_empty : std_logic;
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signal s_receive_fifo_empty : std_logic;
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signal s_receive_fifo_full : std_logic;
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signal s_receive_fifo_full : std_logic;
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signal s_receive_fifo_reset : std_logic;
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signal s_receive_fifo_reset : std_logic;
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signal s_receive_transfersize_en : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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signal s_receive_transfersize_en : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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signal s_receive_counter_load : std_logic;
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signal s_receive_counter_load : std_logic;
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signal s_receive_counter_en : std_logic;
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signal s_receive_counter_en : std_logic;
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signal s_receive_counter_zero : std_logic;
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signal s_receive_counter_zero : std_logic;
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|
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signal s_dev_dep_msg_out : std_logic;
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signal s_dev_dep_msg_out : std_logic;
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signal s_request_dev_dep_msg_in : std_logic;
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signal s_request_dev_dep_msg_in : std_logic;
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signal s_btag_reg_en : std_logic;
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signal s_btag_reg_en : std_logic;
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signal s_nbtag_reg_en : std_logic;
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signal s_nbtag_reg_en : std_logic;
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signal s_btag_correct : std_logic;
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signal s_btag_correct : std_logic;
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signal s_eom_bit_detected : std_logic;
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signal s_eom_bit_detected : std_logic;
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|
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signal s_send_fifo_rd_en : std_logic;
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signal s_send_fifo_rd_en : std_logic;
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signal s_send_fifo_empty : std_logic;
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signal s_send_fifo_empty : std_logic;
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signal s_send_fifo_reset : std_logic;
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signal s_send_fifo_reset : std_logic;
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signal s_send_counter_load : std_logic;
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signal s_send_counter_load : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_zero : std_logic;
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signal s_send_counter_zero : std_logic;
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signal s_send_mux_sel : std_logic_vector(2 downto 0);
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signal s_send_mux_sel : std_logic_vector(2 downto 0);
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|
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signal s_receive_newdata_set : std_logic;
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signal s_receive_newdata_set : std_logic;
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signal s_receive_end_of_message_set : std_logic;
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signal s_receive_end_of_message_set : std_logic;
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signal s_send_data_request_set : std_logic;
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signal s_send_data_request_set : std_logic;
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begin -- behaviour
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begin -- behaviour
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GPIF_INTERFACE: gpif_com
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GPIF_INTERFACE: gpif_com
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port map (
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port map (
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i_nReset => i_nReset,
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i_nReset => i_nReset,
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i_SYSCLK => i_sysclk,
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i_SYSCLK => i_sysclk,
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o_ABORT => s_gpif_abort,
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o_ABORT => s_gpif_abort,
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o_RX => s_gpif_rx,
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o_RX => s_gpif_rx,
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o_TX => s_gpif_tx,
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o_TX => s_gpif_tx,
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i_RD_EN => s_gpif_rx_rd_en,
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i_RD_EN => s_gpif_rx_rd_en,
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o_EMPTY => s_gpif_rx_empty,
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o_EMPTY => s_gpif_rx_empty,
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o_RX_DATA => s_gpif_rx_data,
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o_RX_DATA => s_gpif_rx_data,
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i_EOM => s_gpif_eom,
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i_EOM => s_gpif_eom,
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i_WR_EN => s_gpif_tx_wr_en,
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i_WR_EN => s_gpif_tx_wr_en,
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o_FULL => s_gpif_tx_full,
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o_FULL => s_gpif_tx_full,
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i_TX_DATA => s_gpif_tx_data,
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i_TX_DATA => s_gpif_tx_data,
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i_IFCLK => i_IFCLK,
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i_IFCLK => i_IFCLK,
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i_WRU => i_WRU,
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i_WRU => i_WRU,
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i_RDYU => i_RDYU,
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i_RDYU => i_RDYU,
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o_WRX => o_WRX,
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o_WRX => o_WRX,
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o_RDYX => o_RDYX,
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o_RDYX => o_RDYX,
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b_gpif_bus => b_gpif_bus);
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b_gpif_bus => b_gpif_bus);
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o_rx <= s_gpif_rx;
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o_rx <= s_gpif_rx;
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o_tx <= s_gpif_tx;
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o_tx <= s_gpif_tx;
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GECKO3COM_simple_datapath_1 : GECKO3COM_simple_datapath
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GECKO3COM_simple_datapath_1 : GECKO3COM_simple_datapath
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generic map (
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generic map (
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BUSWIDTH => BUSWIDTH)
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BUSWIDTH => BUSWIDTH)
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port map (
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port map (
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i_nReset => i_nReset,
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i_nReset => i_nReset,
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i_sysclk => i_sysclk,
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i_sysclk => i_sysclk,
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i_rx_data => s_gpif_rx_data,
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i_rx_data => s_gpif_rx_data,
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o_tx_data => s_gpif_tx_data,
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o_tx_data => s_gpif_tx_data,
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i_receive_fifo_rd_en => i_receive_fifo_rd_en,
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i_receive_fifo_rd_en => i_receive_fifo_rd_en,
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i_receive_fifo_wr_en => s_receive_fifo_wr_en,
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i_receive_fifo_wr_en => s_receive_fifo_wr_en,
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o_receive_fifo_empty => s_receive_fifo_empty,
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o_receive_fifo_empty => s_receive_fifo_empty,
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o_receive_fifo_full => s_receive_fifo_full,
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o_receive_fifo_full => s_receive_fifo_full,
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o_receive_fifo_data => o_receive_fifo_data,
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o_receive_fifo_data => o_receive_fifo_data,
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i_receive_fifo_reset => s_receive_fifo_reset,
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i_receive_fifo_reset => s_receive_fifo_reset,
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o_receive_transfersize => o_receive_transfersize,
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o_receive_transfersize => o_receive_transfersize,
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i_receive_transfersize_en => s_receive_transfersize_en,
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i_receive_transfersize_en => s_receive_transfersize_en,
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i_receive_counter_load => s_receive_counter_load,
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i_receive_counter_load => s_receive_counter_load,
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i_receive_counter_en => s_receive_counter_en,
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i_receive_counter_en => s_receive_counter_en,
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o_receive_counter_zero => s_receive_counter_zero,
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o_receive_counter_zero => s_receive_counter_zero,
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o_dev_dep_msg_out => s_dev_dep_msg_out,
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o_dev_dep_msg_out => s_dev_dep_msg_out,
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o_request_dev_dep_msg_in => s_request_dev_dep_msg_in,
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o_request_dev_dep_msg_in => s_request_dev_dep_msg_in,
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i_btag_reg_en => s_btag_reg_en,
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i_btag_reg_en => s_btag_reg_en,
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i_nbtag_reg_en => s_nbtag_reg_en,
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i_nbtag_reg_en => s_nbtag_reg_en,
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o_btag_correct => s_btag_correct,
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o_btag_correct => s_btag_correct,
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o_eom_bit_detected => s_eom_bit_detected,
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o_eom_bit_detected => s_eom_bit_detected,
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i_send_fifo_rd_en => s_send_fifo_rd_en,
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i_send_fifo_rd_en => s_send_fifo_rd_en,
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i_send_fifo_wr_en => i_send_fifo_wr_en,
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i_send_fifo_wr_en => i_send_fifo_wr_en,
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o_send_fifo_empty => s_send_fifo_empty,
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o_send_fifo_empty => s_send_fifo_empty,
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o_send_fifo_full => o_send_fifo_full,
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o_send_fifo_full => o_send_fifo_full,
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i_send_fifo_data => i_send_fifo_data,
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i_send_fifo_data => i_send_fifo_data,
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i_send_fifo_reset => s_send_fifo_reset,
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i_send_fifo_reset => s_send_fifo_reset,
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i_send_transfersize => i_send_transfersize,
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i_send_transfersize => i_send_transfersize,
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i_send_transfersize_en => i_send_transfersize_en,
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i_send_transfersize_en => i_send_transfersize_en,
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i_send_have_more_data => i_send_have_more_data,
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i_send_have_more_data => i_send_have_more_data,
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i_send_counter_load => s_send_counter_load,
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i_send_counter_load => s_send_counter_load,
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i_send_counter_en => s_send_counter_en,
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i_send_counter_en => s_send_counter_en,
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o_send_counter_zero => s_send_counter_zero,
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o_send_counter_zero => s_send_counter_zero,
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i_send_mux_sel => s_send_mux_sel,
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i_send_mux_sel => s_send_mux_sel,
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i_receive_newdata_set => s_receive_newdata_set,
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i_receive_newdata_set => s_receive_newdata_set,
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o_receive_newdata => o_receive_newdata,
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o_receive_newdata => o_receive_newdata,
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i_receive_end_of_message_set => s_receive_end_of_message_set,
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i_receive_end_of_message_set => s_receive_end_of_message_set,
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o_receive_end_of_message => o_receive_end_of_message,
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o_receive_end_of_message => o_receive_end_of_message,
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i_send_data_request_set => s_send_data_request_set,
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i_send_data_request_set => s_send_data_request_set,
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o_send_data_request => o_send_data_request);
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o_send_data_request => o_send_data_request);
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o_receive_fifo_empty <= s_receive_fifo_empty;
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o_receive_fifo_empty <= s_receive_fifo_empty;
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GECKO3COM_simple_fsm_1: GECKO3COM_simple_fsm
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GECKO3COM_simple_fsm_1: GECKO3COM_simple_fsm
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port map (
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port map (
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i_nReset => i_nReset,
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i_nReset => i_nReset,
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i_sysclk => i_sysclk,
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i_sysclk => i_sysclk,
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o_receive_fifo_wr_en => s_receive_fifo_wr_en,
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o_receive_fifo_wr_en => s_receive_fifo_wr_en,
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i_receive_fifo_full => s_receive_fifo_full,
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i_receive_fifo_full => s_receive_fifo_full,
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o_receive_fifo_reset => s_receive_fifo_reset,
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o_receive_fifo_reset => s_receive_fifo_reset,
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o_receive_transfersize_en => s_receive_transfersize_en,
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o_receive_transfersize_en => s_receive_transfersize_en,
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o_receive_counter_load => s_receive_counter_load,
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o_receive_counter_load => s_receive_counter_load,
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o_receive_counter_en => s_receive_counter_en,
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o_receive_counter_en => s_receive_counter_en,
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i_receive_counter_zero => s_receive_counter_zero,
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i_receive_counter_zero => s_receive_counter_zero,
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i_dev_dep_msg_out => s_dev_dep_msg_out,
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i_dev_dep_msg_out => s_dev_dep_msg_out,
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i_request_dev_dep_msg_in => s_request_dev_dep_msg_in,
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i_request_dev_dep_msg_in => s_request_dev_dep_msg_in,
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o_btag_reg_en => s_btag_reg_en,
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o_btag_reg_en => s_btag_reg_en,
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o_nbtag_reg_en => s_nbtag_reg_en,
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o_nbtag_reg_en => s_nbtag_reg_en,
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i_btag_correct => s_btag_correct,
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i_btag_correct => s_btag_correct,
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i_eom_bit_detected => s_eom_bit_detected,
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i_eom_bit_detected => s_eom_bit_detected,
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i_send_transfersize_en => i_send_transfersize_en,
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i_send_transfersize_en => i_send_transfersize_en,
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o_send_fifo_rd_en => s_send_fifo_rd_en,
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o_send_fifo_rd_en => s_send_fifo_rd_en,
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i_send_fifo_empty => s_send_fifo_empty,
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i_send_fifo_empty => s_send_fifo_empty,
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o_send_fifo_reset => s_send_fifo_reset,
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o_send_fifo_reset => s_send_fifo_reset,
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o_send_counter_load => s_send_counter_load,
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o_send_counter_load => s_send_counter_load,
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o_send_counter_en => s_send_counter_en,
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o_send_counter_en => s_send_counter_en,
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i_send_counter_zero => s_send_counter_zero,
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i_send_counter_zero => s_send_counter_zero,
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o_send_mux_sel => s_send_mux_sel,
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o_send_mux_sel => s_send_mux_sel,
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o_send_finished => o_send_finished,
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o_receive_newdata_set => s_receive_newdata_set,
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o_receive_newdata_set => s_receive_newdata_set,
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o_receive_end_of_message_set => s_receive_end_of_message_set,
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o_receive_end_of_message_set => s_receive_end_of_message_set,
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o_send_data_request_set => s_send_data_request_set,
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o_send_data_request_set => s_send_data_request_set,
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i_gpif_rx => s_gpif_rx,
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i_gpif_rx => s_gpif_rx,
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i_gpif_rx_empty => s_gpif_rx_empty,
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i_gpif_rx_empty => s_gpif_rx_empty,
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o_gpif_rx_rd_en => s_gpif_rx_rd_en,
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o_gpif_rx_rd_en => s_gpif_rx_rd_en,
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i_gpif_tx => s_gpif_tx,
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i_gpif_tx => s_gpif_tx,
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i_gpif_tx_full => s_gpif_tx_full,
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i_gpif_tx_full => s_gpif_tx_full,
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o_gpif_tx_wr_en => s_gpif_tx_wr_en,
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o_gpif_tx_wr_en => s_gpif_tx_wr_en,
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i_gpif_abort => s_gpif_abort,
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i_gpif_abort => s_gpif_abort,
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o_gpif_eom => s_gpif_eom);
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o_gpif_eom => s_gpif_eom);
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end Behavioral;
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end Behavioral;
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