-- GECKO3COM IP Core
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-- GECKO3COM IP Core
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--
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--
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-- Copyright (C) 2009 by
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-- Copyright (C) 2009 by
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-- ___ ___ _ _
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-- ___ ___ _ _
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-- ( _ \ ( __)( ) ( )
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-- ( _ \ ( __)( ) ( )
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | _ < | _) | _ | School of Engineering and
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-- | _ < | _) | _ | School of Engineering and
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-- | (_) )| | | | | | Information Technology
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-- | (_) )| | | | | | Information Technology
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-- (____/ (_) (_) (_)
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-- (____/ (_) (_) (_)
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- URL to the project description:
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-- URL to the project description:
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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--
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-- Author: Christoph Zimmermann
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-- Author: Christoph Zimmermann
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-- Date of creation: 3 february 2010
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-- Date of creation: 3 february 2010
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-- Description:
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-- Description:
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-- This is the finite-state-mashine for the GECKO3com simple IP core.
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-- This is the finite-state-mashine for the GECKO3com simple IP core.
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--
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--
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-- This core provides a simple FIFO and register interface to the
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-- This core provides a simple FIFO and register interface to the
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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--
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--
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-- Look at GECKO3COM_simple_test.vhd for an example how to use it.
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-- Look at GECKO3COM_simple_test.vhd for an example how to use it.
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--
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--
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-- Target Devices: general
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-- Target Devices: general
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-- Tool versions: 11.1
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-- Tool versions: 11.1
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library work;
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library work;
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use work.GECKO3COM_defines.all;
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use work.GECKO3COM_defines.all;
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entity GECKO3COM_simple_fsm is
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entity GECKO3COM_simple_fsm is
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_sysclk : in std_logic;
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i_sysclk : in std_logic;
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o_receive_fifo_wr_en : out std_logic;
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o_receive_fifo_wr_en : out std_logic;
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i_receive_fifo_full : in std_logic;
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i_receive_fifo_full : in std_logic;
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o_receive_fifo_reset : out std_logic;
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o_receive_fifo_reset : out std_logic;
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o_receive_transfersize_en : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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o_receive_transfersize_en : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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i_receive_transfersize_lsb : in std_logic;
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i_receive_transfersize_lsb : in std_logic;
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o_receive_counter_load : out std_logic;
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o_receive_counter_load : out std_logic;
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o_receive_counter_en : out std_logic;
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o_receive_counter_en : out std_logic;
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i_receive_counter_zero : in std_logic;
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i_receive_counter_zero : in std_logic;
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i_dev_dep_msg_out : in std_logic;
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i_dev_dep_msg_out : in std_logic;
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i_request_dev_dep_msg_in : in std_logic;
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i_request_dev_dep_msg_in : in std_logic;
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o_btag_reg_en : out std_logic;
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o_btag_reg_en : out std_logic;
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o_nbtag_reg_en : out std_logic;
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o_nbtag_reg_en : out std_logic;
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i_btag_correct : in std_logic;
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i_btag_correct : in std_logic;
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i_eom_bit_detected : in std_logic;
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i_eom_bit_detected : in std_logic;
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i_send_transfersize_en : in std_logic;
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i_send_transfersize_en : in std_logic;
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o_send_fifo_rd_en : out std_logic;
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o_send_fifo_rd_en : out std_logic;
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i_send_fifo_empty : in std_logic;
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i_send_fifo_empty : in std_logic;
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o_send_fifo_reset : out std_logic;
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o_send_fifo_reset : out std_logic;
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o_send_counter_load : out std_logic;
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o_send_counter_load : out std_logic;
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o_send_counter_en : out std_logic;
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o_send_counter_en : out std_logic;
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i_send_counter_zero : in std_logic;
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i_send_counter_zero : in std_logic;
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o_send_mux_sel : out std_logic_vector(2 downto 0);
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o_send_mux_sel : out std_logic_vector(2 downto 0);
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o_send_finished : out std_logic;
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o_send_finished : out std_logic;
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o_receive_newdata_set : out std_logic;
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o_receive_newdata_set : out std_logic;
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o_receive_end_of_message_set : out std_logic;
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o_receive_end_of_message_set : out std_logic;
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o_send_data_request_set : out std_logic;
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o_send_data_request_set : out std_logic;
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i_gpif_rx : in std_logic;
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i_gpif_rx : in std_logic;
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i_gpif_rx_empty : in std_logic;
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i_gpif_rx_empty : in std_logic;
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o_gpif_rx_rd_en : out std_logic;
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o_gpif_rx_rd_en : out std_logic;
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i_gpif_tx : in std_logic;
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i_gpif_tx : in std_logic;
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i_gpif_tx_full : in std_logic;
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i_gpif_tx_full : in std_logic;
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o_gpif_tx_wr_en : out std_logic;
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o_gpif_tx_wr_en : out std_logic;
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i_gpif_abort : in std_logic;
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i_gpif_abort : in std_logic;
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o_gpif_eom : out std_logic);
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o_gpif_eom : out std_logic);
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end GECKO3COM_simple_fsm;
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end GECKO3COM_simple_fsm;
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architecture fsm of GECKO3COM_simple_fsm is
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architecture fsm of GECKO3COM_simple_fsm is
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-- XST specific synthesize attributes
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-- XST specific synthesize attributes
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attribute safe_implementation : string;
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attribute safe_implementation : string;
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attribute safe_recovery_state : string;
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attribute safe_recovery_state : string;
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attribute fsm_encoding : string;
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type state_type is (st1_idle, st2_abort, st3_read_msg_id, st4_check_msg_id,
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type state_type is (st1_idle, st2_abort, st3_read_msg_id, st4_check_msg_id,
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st5_read_nbtag, st6_read_transfer_size_low,
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st5_read_nbtag, st6_read_transfer_size_low,
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st7_read_transfer_size_high, st8_check_attributes,
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st7_read_transfer_size_high, st8_check_attributes,
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st9_signal_data_request, st10_signal_receive_new_data,
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st9_signal_data_request, st10_signal_receive_new_data,
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st11_receive_data, st12_receive_wait,
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st11_receive_data, st12_receive_wait,
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st13_wait_for_receive_end, st14_read_align_bytes,
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st13_wait_for_receive_end, st14_read_align_bytes,
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st15_start_response, st16_send_msg_id,
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st15_start_response, st16_send_msg_id,
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st17_send_nbtag, st18_send_transfer_size_low,
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st17_send_nbtag, st18_send_transfer_size_low,
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st19_send_transfer_size_high, st20_send_attributes,
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st19_send_transfer_size_high, st20_send_attributes,
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st21_send_reserved, st22_send_data, st23_send_wait,
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st21_send_reserved, st22_send_data, st23_send_wait,
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st24_wait_for_send_end);
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st24_wait_for_send_end);
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signal state, next_state : state_type;
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signal state, next_state : state_type;
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-- XST specific synthesize attributes
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-- XST specific synthesize attributes
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attribute safe_recovery_state of state : signal is "st1_idle";
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attribute safe_recovery_state of state : signal is "st1_idle";
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attribute safe_implementation of state : signal is "yes";
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attribute safe_implementation of state : signal is "yes";
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attribute fsm_encoding of state : signal is "johnson";
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--Declare internal signals for all outputs of the state-machine
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--Declare internal signals for all outputs of the state-machine
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signal s_receive_fifo_wr_en : std_logic;
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signal s_receive_fifo_wr_en : std_logic;
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signal s_receive_fifo_reset : std_logic;
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signal s_receive_fifo_reset : std_logic;
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signal s_receive_transfersize_en : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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signal s_receive_transfersize_en : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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signal s_receive_counter_load : std_logic;
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signal s_receive_counter_load : std_logic;
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signal s_receive_counter_en : std_logic;
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signal s_receive_counter_en : std_logic;
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signal s_btag_reg_en : std_logic;
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signal s_btag_reg_en : std_logic;
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signal s_nbtag_reg_en : std_logic;
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signal s_nbtag_reg_en : std_logic;
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signal s_send_fifo_rd_en : std_logic;
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signal s_send_fifo_rd_en : std_logic;
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signal s_send_fifo_reset : std_logic;
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signal s_send_fifo_reset : std_logic;
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signal s_send_counter_load : std_logic;
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signal s_send_counter_load : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_mux_sel : std_logic_vector(2 downto 0);
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signal s_send_mux_sel : std_logic_vector(2 downto 0);
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signal s_send_finished : std_logic;
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signal s_send_finished : std_logic;
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signal s_receive_newdata_set : std_logic;
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signal s_receive_newdata_set : std_logic;
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signal s_receive_end_of_message_set : std_logic;
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signal s_receive_end_of_message_set : std_logic;
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signal s_send_data_request_set : std_logic;
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signal s_send_data_request_set : std_logic;
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signal s_gpif_eom : std_logic;
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signal s_gpif_eom : std_logic;
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signal s_gpif_rx_rd_en : std_logic;
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signal s_gpif_rx_rd_en : std_logic;
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signal s_gpif_tx_wr_en : std_logic;
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signal s_gpif_tx_wr_en : std_logic;
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begin -- fsm
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begin -- fsm
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o_receive_fifo_wr_en <= s_receive_fifo_wr_en;
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o_receive_fifo_wr_en <= s_receive_fifo_wr_en;
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o_receive_fifo_reset <= s_receive_fifo_reset;
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o_receive_fifo_reset <= s_receive_fifo_reset;
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o_receive_transfersize_en <= s_receive_transfersize_en;
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o_receive_transfersize_en <= s_receive_transfersize_en;
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o_receive_counter_load <= s_receive_counter_load;
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o_receive_counter_load <= s_receive_counter_load;
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o_receive_counter_en <= s_receive_counter_en;
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o_receive_counter_en <= s_receive_counter_en;
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o_btag_reg_en <= s_btag_reg_en;
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o_btag_reg_en <= s_btag_reg_en;
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o_nbtag_reg_en <= s_nbtag_reg_en;
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o_nbtag_reg_en <= s_nbtag_reg_en;
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o_send_fifo_rd_en <= s_send_fifo_rd_en;
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o_send_fifo_rd_en <= s_send_fifo_rd_en;
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o_send_fifo_reset <= s_send_fifo_reset;
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o_send_fifo_reset <= s_send_fifo_reset;
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o_send_counter_load <= s_send_counter_load;
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o_send_counter_load <= s_send_counter_load;
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o_send_counter_en <= s_send_counter_en;
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o_send_counter_en <= s_send_counter_en;
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o_send_mux_sel <= s_send_mux_sel;
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o_send_mux_sel <= s_send_mux_sel;
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o_send_finished <= s_send_finished;
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o_send_finished <= s_send_finished;
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o_receive_newdata_set <= s_receive_newdata_set;
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o_receive_newdata_set <= s_receive_newdata_set;
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o_receive_end_of_message_set <= s_receive_end_of_message_set;
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o_receive_end_of_message_set <= s_receive_end_of_message_set;
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o_send_data_request_set <= s_send_data_request_set;
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o_send_data_request_set <= s_send_data_request_set;
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o_gpif_eom <= s_gpif_eom;
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o_gpif_eom <= s_gpif_eom;
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o_gpif_rx_rd_en <= s_gpif_rx_rd_en;
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o_gpif_rx_rd_en <= s_gpif_rx_rd_en;
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o_gpif_tx_wr_en <= s_gpif_tx_wr_en;
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o_gpif_tx_wr_en <= s_gpif_tx_wr_en;
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SYNC_PROC : process (i_sysclk)
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SYNC_PROC : process (i_sysclk)
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begin
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begin
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if (i_sysclk'event and i_sysclk = '1') then
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if (i_sysclk'event and i_sysclk = '1') then
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if (i_nReset = '0') then
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if (i_nReset = '0') then
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state <= st1_idle;
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state <= st1_idle;
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else
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else
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state <= next_state;
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state <= next_state;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--MEALY State-Machine - Outputs based on state and inputs
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--MEALY State-Machine - Outputs based on state and inputs
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OUTPUT_DECODE : process (state, i_receive_fifo_full,
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OUTPUT_DECODE : process (state, i_receive_fifo_full,
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i_receive_counter_zero, i_dev_dep_msg_out,
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i_receive_counter_zero, i_dev_dep_msg_out,
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i_request_dev_dep_msg_in, --i_btag_correct,
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i_request_dev_dep_msg_in, --i_btag_correct,
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i_eom_bit_detected, i_send_transfersize_en,
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i_eom_bit_detected, i_send_transfersize_en,
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i_send_fifo_empty, i_send_counter_zero,
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i_send_fifo_empty, i_send_counter_zero,
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i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
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i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
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i_gpif_tx_full, i_gpif_abort,
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i_gpif_tx_full, i_gpif_abort,
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i_receive_transfersize_lsb)
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i_receive_transfersize_lsb)
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begin
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begin
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s_receive_fifo_wr_en <= '0';
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s_receive_fifo_wr_en <= '0';
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s_receive_fifo_reset <= '0';
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s_receive_fifo_reset <= '0';
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s_receive_transfersize_en <= (others => '0');
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s_receive_transfersize_en <= (others => '0');
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s_receive_counter_load <= '0';
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s_receive_counter_load <= '0';
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s_receive_counter_en <= '0';
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s_receive_counter_en <= '0';
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s_btag_reg_en <= '0';
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s_btag_reg_en <= '0';
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s_nbtag_reg_en <= '0';
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s_nbtag_reg_en <= '0';
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s_send_fifo_rd_en <= '0';
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s_send_fifo_rd_en <= '0';
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s_send_fifo_reset <= '0';
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s_send_fifo_reset <= '0';
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s_send_counter_load <= '0';
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s_send_counter_load <= '0';
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s_send_counter_en <= '0';
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s_send_counter_en <= '0';
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s_send_mux_sel <= (others => '0');
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s_send_mux_sel <= (others => '0');
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s_send_finished <= '0';
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s_send_finished <= '0';
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s_receive_newdata_set <= '0';
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s_receive_newdata_set <= '0';
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s_receive_end_of_message_set <= '0';
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s_receive_end_of_message_set <= '0';
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s_send_data_request_set <= '0';
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s_send_data_request_set <= '0';
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s_gpif_eom <= '0';
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s_gpif_eom <= '0';
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s_gpif_rx_rd_en <= '0';
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s_gpif_rx_rd_en <= '0';
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s_gpif_tx_wr_en <= '0';
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s_gpif_tx_wr_en <= '0';
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if state = st11_receive_data then
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if state = st11_receive_data then
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s_receive_fifo_wr_en <= '1';
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s_receive_fifo_wr_en <= '1';
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end if;
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end if;
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if state = st2_abort then
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if state = st2_abort then
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s_receive_fifo_reset <= '1';
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s_receive_fifo_reset <= '1';
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end if;
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end if;
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if state = st6_read_transfer_size_low then
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if state = st6_read_transfer_size_low then
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s_receive_transfersize_en <= "01";
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s_receive_transfersize_en <= "01";
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elsif state = st7_read_transfer_size_high then
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elsif state = st7_read_transfer_size_high then
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s_receive_transfersize_en <= "10";
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s_receive_transfersize_en <= "10";
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end if;
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end if;
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if state = st8_check_attributes and
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if state = st8_check_attributes and
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i_dev_dep_msg_out = '1' and
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i_dev_dep_msg_out = '1' and
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i_gpif_rx_empty = '0'
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i_gpif_rx_empty = '0'
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then
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then
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s_receive_counter_load <= '1';
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s_receive_counter_load <= '1';
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end if;
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end if;
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if (state = st10_signal_receive_new_data and
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if (state = st10_signal_receive_new_data and
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i_gpif_rx_empty = '0' and
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i_gpif_rx_empty = '0' and
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i_receive_fifo_full = '0' and
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i_receive_fifo_full = '0' and
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i_receive_transfersize_lsb = '0') -- if it is '1' then we have to read
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i_receive_transfersize_lsb = '0') -- if it is '1' then we have to read
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-- one time more from the fifo (which
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-- one time more from the fifo (which
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-- is 16bit wide)
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-- is 16bit wide)
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or (state = st11_receive_data and
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or (state = st11_receive_data and
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i_receive_counter_zero = '0' and
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i_receive_counter_zero = '0' and
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i_gpif_rx_empty = '0' and
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i_gpif_rx_empty = '0' and
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i_receive_fifo_full = '0')
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i_receive_fifo_full = '0')
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or (state = st12_receive_wait and
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or (state = st12_receive_wait and
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i_gpif_rx_empty = '0' and
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i_gpif_rx_empty = '0' and
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i_receive_fifo_full = '0')
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i_receive_fifo_full = '0')
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then
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then
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s_receive_counter_en <= '1';
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s_receive_counter_en <= '1';
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end if;
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end if;
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if state = st3_read_msg_id then
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if state = st3_read_msg_id then
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s_btag_reg_en <= '1';
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s_btag_reg_en <= '1';
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end if;
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end if;
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if state = st5_read_nbtag then
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if state = st5_read_nbtag then
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s_nbtag_reg_en <= '1';
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s_nbtag_reg_en <= '1';
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end if;
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end if;
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if (state = st21_send_reserved and
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if (state = st21_send_reserved and
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i_gpif_tx_full = '0' and
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i_gpif_tx_full = '0' and
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i_send_fifo_empty = '0')
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i_send_fifo_empty = '0')
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or (state = st22_send_data and
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or (state = st22_send_data and
|
i_gpif_tx_full = '0' and
|
i_gpif_tx_full = '0' and
|
i_send_fifo_empty = '0' and
|
i_send_fifo_empty = '0' and
|
i_send_counter_zero = '0')
|
i_send_counter_zero = '0')
|
or (state = st23_send_wait and
|
or (state = st23_send_wait and
|
i_gpif_tx_full = '0' and
|
i_gpif_tx_full = '0' and
|
i_send_fifo_empty = '0')
|
i_send_fifo_empty = '0')
|
then
|
then
|
s_send_fifo_rd_en <= '1';
|
s_send_fifo_rd_en <= '1';
|
end if;
|
end if;
|
|
|
if state = st2_abort or state = st24_wait_for_send_end then
|
if state = st2_abort or state = st24_wait_for_send_end then
|
s_send_fifo_reset <= '1';
|
s_send_fifo_reset <= '1';
|
end if;
|
end if;
|
|
|
if state = st20_send_attributes then
|
if state = st20_send_attributes then
|
s_send_counter_load <= '1';
|
s_send_counter_load <= '1';
|
end if;
|
end if;
|
|
|
if (state = st21_send_reserved and i_gpif_tx_full = '0' and
|
if (state = st21_send_reserved and i_gpif_tx_full = '0' and
|
i_send_fifo_empty = '0')
|
i_send_fifo_empty = '0')
|
or (state = st22_send_data and
|
or (state = st22_send_data and
|
i_gpif_tx_full = '0' and
|
i_gpif_tx_full = '0' and
|
i_send_fifo_empty = '0' and
|
i_send_fifo_empty = '0' and
|
i_send_counter_zero = '0')
|
i_send_counter_zero = '0')
|
or (state = st23_send_wait and
|
or (state = st23_send_wait and
|
i_gpif_tx_full = '0' and
|
i_gpif_tx_full = '0' and
|
i_send_fifo_empty = '0')
|
i_send_fifo_empty = '0')
|
then
|
then
|
s_send_counter_en <= '1';
|
s_send_counter_en <= '1';
|
end if;
|
end if;
|
|
|
if state = st16_send_msg_id then
|
if state = st16_send_msg_id then
|
s_send_mux_sel <= "000";
|
s_send_mux_sel <= "000";
|
elsif state = st17_send_nbtag then
|
elsif state = st17_send_nbtag then
|
s_send_mux_sel <= "001";
|
s_send_mux_sel <= "001";
|
elsif state =st18_send_transfer_size_low then
|
elsif state =st18_send_transfer_size_low then
|
s_send_mux_sel <= "010";
|
s_send_mux_sel <= "010";
|
elsif state = st19_send_transfer_size_high then
|
elsif state = st19_send_transfer_size_high then
|
s_send_mux_sel <= "011";
|
s_send_mux_sel <= "011";
|
elsif state = st20_send_attributes then
|
elsif state = st20_send_attributes then
|
s_send_mux_sel <= "100";
|
s_send_mux_sel <= "100";
|
elsif state = st21_send_reserved then
|
elsif state = st21_send_reserved then
|
s_send_mux_sel <= "101";
|
s_send_mux_sel <= "101";
|
elsif state = st22_send_data or state = st23_send_wait then
|
elsif state = st22_send_data or state = st23_send_wait then
|
s_send_mux_sel <= "110";
|
s_send_mux_sel <= "110";
|
end if;
|
end if;
|
|
|
if state = st24_wait_for_send_end and i_gpif_tx = '0' then
|
if state = st24_wait_for_send_end and i_gpif_tx = '0' then
|
s_send_finished <= '1';
|
s_send_finished <= '1';
|
end if;
|
end if;
|
|
|
if state = st10_signal_receive_new_data then
|
if state = st10_signal_receive_new_data then
|
s_receive_newdata_set <= '1';
|
s_receive_newdata_set <= '1';
|
end if;
|
end if;
|
|
|
if state = st8_check_attributes and i_eom_bit_detected = '1' then
|
if state = st8_check_attributes and i_eom_bit_detected = '1' then
|
s_receive_end_of_message_set <= '1';
|
s_receive_end_of_message_set <= '1';
|
end if;
|
end if;
|
|
|
if state = st9_signal_data_request then
|
if state = st9_signal_data_request then
|
s_send_data_request_set <= '1';
|
s_send_data_request_set <= '1';
|
end if;
|
end if;
|
|
|
if (state = st22_send_data and i_send_counter_zero = '1')
|
if (state = st22_send_data and i_send_counter_zero = '1')
|
or state = st24_wait_for_send_end
|
or state = st24_wait_for_send_end
|
then
|
then
|
s_gpif_eom <= '1';
|
s_gpif_eom <= '1';
|
end if;
|
end if;
|
|
|
if (i_gpif_rx_empty = '0' and
|
if (i_gpif_rx_empty = '0' and
|
(state = st1_idle or
|
(state = st1_idle or
|
state = st5_read_nbtag or
|
state = st5_read_nbtag or
|
state = st6_read_transfer_size_low or
|
state = st6_read_transfer_size_low or
|
state = st7_read_transfer_size_high or
|
state = st7_read_transfer_size_high or
|
state = st8_check_attributes))
|
state = st8_check_attributes))
|
or (state = st4_check_msg_id and
|
or (state = st4_check_msg_id and
|
i_gpif_rx_empty = '0' and
|
i_gpif_rx_empty = '0' and
|
(i_dev_dep_msg_out = '1' or i_request_dev_dep_msg_in = '1'))
|
(i_dev_dep_msg_out = '1' or i_request_dev_dep_msg_in = '1'))
|
or ((state = st10_signal_receive_new_data or state = st12_receive_wait)
|
or ((state = st10_signal_receive_new_data or state = st12_receive_wait)
|
and i_gpif_rx_empty = '0' and i_receive_fifo_full = '0')
|
and i_gpif_rx_empty = '0' and i_receive_fifo_full = '0')
|
or (state = st11_receive_data and
|
or (state = st11_receive_data and
|
i_receive_counter_zero = '0' and
|
i_receive_counter_zero = '0' and
|
i_gpif_rx_empty = '0' and
|
i_gpif_rx_empty = '0' and
|
i_receive_fifo_full = '0')
|
i_receive_fifo_full = '0')
|
or (state = st12_receive_wait and
|
or (state = st12_receive_wait and
|
i_gpif_rx_empty = '0' and
|
i_gpif_rx_empty = '0' and
|
i_receive_fifo_full = '0')
|
i_receive_fifo_full = '0')
|
or (state = st14_read_align_bytes and i_gpif_rx_empty = '0')
|
or (state = st14_read_align_bytes and i_gpif_rx_empty = '0')
|
then
|
then
|
s_gpif_rx_rd_en <= '1';
|
s_gpif_rx_rd_en <= '1';
|
end if;
|
end if;
|
|
|
if (i_gpif_tx_full = '0' and
|
if (i_gpif_tx_full = '0' and
|
(state = st16_send_msg_id or
|
(state = st16_send_msg_id or
|
state = st17_send_nbtag or
|
state = st17_send_nbtag or
|
state = st18_send_transfer_size_low or
|
state = st18_send_transfer_size_low or
|
state = st19_send_transfer_size_high or
|
state = st19_send_transfer_size_high or
|
state = st20_send_attributes or
|
state = st20_send_attributes or
|
state = st21_send_reserved))
|
state = st21_send_reserved))
|
or state = st22_send_data
|
or (state = st22_send_data and
|
|
i_gpif_tx_full = '0' and
|
|
i_send_fifo_empty = '0')
|
|
or (state = st23_send_wait and
|
|
i_gpif_tx_full = '0' and
|
|
i_send_fifo_empty = '0')
|
then
|
then
|
s_gpif_tx_wr_en <= '1';
|
s_gpif_tx_wr_en <= '1';
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
NEXT_STATE_DECODE : process (state, i_receive_fifo_full,
|
NEXT_STATE_DECODE : process (state, i_receive_fifo_full,
|
i_receive_counter_zero, i_dev_dep_msg_out,
|
i_receive_counter_zero, i_dev_dep_msg_out,
|
i_request_dev_dep_msg_in, i_btag_correct,
|
i_request_dev_dep_msg_in, i_btag_correct,
|
i_eom_bit_detected, i_send_transfersize_en,
|
i_eom_bit_detected, i_send_transfersize_en,
|
i_send_fifo_empty, i_send_counter_zero,
|
i_send_fifo_empty, i_send_counter_zero,
|
i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
|
i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
|
i_gpif_tx_full, i_gpif_abort)
|
i_gpif_tx_full, i_gpif_abort)
|
begin
|
begin
|
--declare default state for next_state to avoid latches
|
--declare default state for next_state to avoid latches
|
next_state <= state; --default is to stay in current state
|
next_state <= state; --default is to stay in current state
|
|
|
case (state) is
|
case (state) is
|
when st1_idle =>
|
when st1_idle =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx_empty = '0' then
|
elsif i_gpif_rx_empty = '0' then
|
next_state <= st3_read_msg_id;
|
next_state <= st3_read_msg_id;
|
end if;
|
end if;
|
|
|
when st2_abort =>
|
when st2_abort =>
|
|
if i_gpif_abort = '0' then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
|
end if;
|
|
|
when st3_read_msg_id =>
|
when st3_read_msg_id =>
|
next_state <= st4_check_msg_id;
|
next_state <= st4_check_msg_id;
|
|
|
when st4_check_msg_id =>
|
when st4_check_msg_id =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_dev_dep_msg_out = '0' and i_request_dev_dep_msg_in = '0' then
|
elsif i_dev_dep_msg_out = '0' and i_request_dev_dep_msg_in = '0' then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
elsif i_gpif_rx_empty = '0' and
|
elsif i_gpif_rx_empty = '0' and
|
(i_dev_dep_msg_out = '1' or i_request_dev_dep_msg_in = '1')
|
(i_dev_dep_msg_out = '1' or i_request_dev_dep_msg_in = '1')
|
then
|
then
|
next_state <= st5_read_nbtag;
|
next_state <= st5_read_nbtag;
|
end if;
|
end if;
|
|
|
when st5_read_nbtag =>
|
when st5_read_nbtag =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx_empty = '0' then
|
elsif i_gpif_rx_empty = '0' then
|
next_state <= st6_read_transfer_size_low;
|
next_state <= st6_read_transfer_size_low;
|
end if;
|
end if;
|
|
|
when st6_read_transfer_size_low =>
|
when st6_read_transfer_size_low =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_btag_correct = '0' then
|
elsif i_btag_correct = '0' then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
elsif i_gpif_rx_empty = '0' and i_btag_correct = '1' then
|
elsif i_gpif_rx_empty = '0' and i_btag_correct = '1' then
|
next_state <= st7_read_transfer_size_high;
|
next_state <= st7_read_transfer_size_high;
|
end if;
|
end if;
|
|
|
when st7_read_transfer_size_high =>
|
when st7_read_transfer_size_high =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx_empty = '0' then
|
elsif i_gpif_rx_empty = '0' then
|
next_state <= st8_check_attributes;
|
next_state <= st8_check_attributes;
|
end if;
|
end if;
|
|
|
when st8_check_attributes =>
|
when st8_check_attributes =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_dev_dep_msg_out = '0' and i_request_dev_dep_msg_in = '0' then
|
elsif i_dev_dep_msg_out = '0' and i_request_dev_dep_msg_in = '0' then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
elsif i_gpif_rx_empty = '0' and i_request_dev_dep_msg_in = '1' then
|
elsif i_gpif_rx_empty = '0' and i_request_dev_dep_msg_in = '1' then
|
next_state <= st9_signal_data_request;
|
next_state <= st9_signal_data_request;
|
elsif i_gpif_rx_empty = '0' and i_dev_dep_msg_out = '1' then
|
elsif i_gpif_rx_empty = '0' and i_dev_dep_msg_out = '1' then
|
next_state <= st10_signal_receive_new_data;
|
next_state <= st10_signal_receive_new_data;
|
end if;
|
end if;
|
|
|
when st9_signal_data_request =>
|
when st9_signal_data_request =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_send_transfersize_en = '1' then
|
elsif i_send_transfersize_en = '1' then
|
next_state <= st15_start_response;
|
next_state <= st15_start_response;
|
end if;
|
end if;
|
|
|
when st10_signal_receive_new_data =>
|
when st10_signal_receive_new_data =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
|
elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
|
next_state <= st11_receive_data;
|
next_state <= st11_receive_data;
|
end if;
|
end if;
|
|
|
when st11_receive_data =>
|
when st11_receive_data =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_receive_counter_zero = '1' then
|
elsif i_receive_counter_zero = '1' then
|
--next_state <= st13_wait_for_receive_end;
|
--next_state <= st13_wait_for_receive_end;
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
elsif i_gpif_rx_empty = '1' or i_receive_fifo_full = '1' then
|
elsif i_gpif_rx_empty = '1' or i_receive_fifo_full = '1' then
|
next_state <= st12_receive_wait;
|
next_state <= st12_receive_wait;
|
end if;
|
end if;
|
|
|
when st12_receive_wait =>
|
when st12_receive_wait =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
|
elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
|
next_state <= st11_receive_data;
|
next_state <= st11_receive_data;
|
end if;
|
end if;
|
|
|
when st13_wait_for_receive_end =>
|
when st13_wait_for_receive_end =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx = '0' then
|
elsif i_gpif_rx = '0' then
|
next_state <= st14_read_align_bytes;
|
next_state <= st14_read_align_bytes;
|
end if;
|
end if;
|
|
|
when st14_read_align_bytes =>
|
when st14_read_align_bytes =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_rx_empty = '1' then
|
elsif i_gpif_rx_empty = '1' then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
end if;
|
end if;
|
|
|
when st15_start_response =>
|
when st15_start_response =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' then
|
elsif i_gpif_tx_full = '0' then
|
next_state <= st16_send_msg_id;
|
next_state <= st16_send_msg_id;
|
end if;
|
end if;
|
|
|
when st16_send_msg_id =>
|
when st16_send_msg_id =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' then
|
elsif i_gpif_tx_full = '0' then
|
next_state <= st17_send_nbtag;
|
next_state <= st17_send_nbtag;
|
end if;
|
end if;
|
|
|
when st17_send_nbtag =>
|
when st17_send_nbtag =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' then
|
elsif i_gpif_tx_full = '0' then
|
next_state <= st18_send_transfer_size_low;
|
next_state <= st18_send_transfer_size_low;
|
end if;
|
end if;
|
|
|
when st18_send_transfer_size_low =>
|
when st18_send_transfer_size_low =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' then
|
elsif i_gpif_tx_full = '0' then
|
next_state <= st19_send_transfer_size_high;
|
next_state <= st19_send_transfer_size_high;
|
end if;
|
end if;
|
|
|
when st19_send_transfer_size_high =>
|
when st19_send_transfer_size_high =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' then
|
elsif i_gpif_tx_full = '0' then
|
next_state <= st20_send_attributes;
|
next_state <= st20_send_attributes;
|
end if;
|
end if;
|
|
|
when st20_send_attributes =>
|
when st20_send_attributes =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' then
|
elsif i_gpif_tx_full = '0' then
|
next_state <= st21_send_reserved;
|
next_state <= st21_send_reserved;
|
end if;
|
end if;
|
|
|
when st21_send_reserved =>
|
when st21_send_reserved =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
|
elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
|
next_state <= st22_send_data;
|
next_state <= st22_send_data;
|
end if;
|
end if;
|
|
|
when st22_send_data =>
|
when st22_send_data =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_send_counter_zero = '1' then
|
elsif i_send_counter_zero = '1' then
|
next_state <= st24_wait_for_send_end;
|
next_state <= st24_wait_for_send_end;
|
elsif i_gpif_tx_full = '1' or i_send_fifo_empty = '1' then
|
elsif i_gpif_tx_full = '1' or i_send_fifo_empty = '1' then
|
next_state <= st23_send_wait;
|
next_state <= st23_send_wait;
|
end if;
|
end if;
|
|
|
when st23_send_wait =>
|
when st23_send_wait =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
|
elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
|
next_state <= st22_send_data;
|
next_state <= st22_send_data;
|
end if;
|
end if;
|
|
|
when st24_wait_for_send_end =>
|
when st24_wait_for_send_end =>
|
if i_gpif_abort = '1' then
|
if i_gpif_abort = '1' then
|
next_state <= st2_abort;
|
next_state <= st2_abort;
|
elsif i_gpif_tx = '0' then
|
elsif i_gpif_tx = '0' then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
end fsm;
|
end fsm;
|
|
|