-- GECKO3COM IP Core
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-- GECKO3COM IP Core
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--
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--
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-- Copyright (C) 2009 by
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-- Copyright (C) 2009 by
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-- ___ ___ _ _
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-- ___ ___ _ _
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-- ( _ \ ( __)( ) ( )
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-- ( _ \ ( __)( ) ( )
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | (_) )| ( | |_| | Bern University of Applied Sciences
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-- | _ < | _) | _ | School of Engineering and
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-- | _ < | _) | _ | School of Engineering and
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-- | (_) )| | | | | | Information Technology
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-- | (_) )| | | | | | Information Technology
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-- (____/ (_) (_) (_)
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-- (____/ (_) (_) (_)
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- URL to the project description:
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-- URL to the project description:
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
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----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Author: Andreas Habegger, Christoph Zimmermann
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-- Author: Andreas Habegger, Christoph Zimmermann
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-- Date of creation: 8. April 2009
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-- Date of creation: 8. April 2009
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-- Description:
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-- Description:
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-- FSM that controls the interface between the EZ-USB (and it's internal GPIF,
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-- FSM that controls the interface between the EZ-USB (and it's internal
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-- General Purpose Interface) and our FPGA. The interface is synchronous, where
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-- GPIF, General Purpose Interface) and our FPGA. The interface is
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-- the GPIF provides the clock. This FSM is synchronous to the GPIF clock, also
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-- synchronous, where the GPIF provides the clock. This FSM is synchronous
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-- this side of the FIFO's.
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-- to the GPIF clock, also this side of the FIFO's.
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--
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--
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-- You can find more detailed information how the interface works in the ../Doc
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-- You can find more detailed information how the interface works in the
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-- folder.
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-- ../Doc folder.
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--
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--
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-- Target Devices: Xilinx Spartan3 FPGA's (usage of BlockRam in the Datapath)
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-- Target Devices: general
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-- Tool versions: 11.1
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-- Tool versions: Xilinx ISE 11.1, XST
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-- Dependencies:
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-- Dependencies:
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--
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--
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----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.GECKO3COM_defines.all;
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use work.GECKO3COM_defines.all;
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entity gpif_com_fsm is
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entity gpif_com_fsm is
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port (
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port (
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i_nReset,
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i_nReset : in std_logic;
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i_IFCLK, -- GPIF CLK (GPIF is Master and provides the clock)
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i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
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i_WRU, -- write from GPIF
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i_WRU : in std_logic; -- write from GPIF
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i_RDYU : in std_logic; -- GPIF is ready
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i_RDYU : in std_logic; -- GPIF is ready
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i_U2X_FULL,
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i_U2X_FULL : in std_logic;
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i_U2X_AM_FULL, -- signals for IN FIFO
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i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
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i_X2U_AM_EMPTY,
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i_X2U_AM_EMPTY : in std_logic;
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
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o_bus_trans_dir : out std_logic;
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o_bus_trans_dir : out std_logic;
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o_U2X_WR_EN, -- signals for IN FIFO
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o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
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o_X2U_RD_EN, -- signals for OUT FIFO
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o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
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o_FIFOrst,
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o_FIFOrst : out std_logic;
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o_WRX, -- To write to GPIF
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o_WRX : out std_logic; -- To write to GPIF
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o_RDYX : out std_logic; -- Core is ready
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o_RDYX : out std_logic; -- Core is ready
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o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
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o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
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o_RX,
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o_RX : out std_logic;
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o_TX : out std_logic --
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o_TX : out std_logic --
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);
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);
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-- XST specific synthesize attributes
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attribute safe_implementation: string;
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attribute safe_recovery_state: string;
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attribute safe_implementation of gpif_com_fsm : entity is "yes";
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end gpif_com_fsm;
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end gpif_com_fsm;
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architecture fsm of gpif_com_fsm is
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architecture fsm of gpif_com_fsm is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- FSM
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-- FSM
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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type t_busAccess is (readFromGPIF, writeToGPIF);
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type t_busAccess is (readFromGPIF, writeToGPIF);
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signal s_bus_trans_dir : t_busAccess;
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signal s_bus_trans_dir : t_busAccess;
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type t_fsmState is (rst, idle, -- controll states
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type t_fsmState is (rst, idle, -- controll states
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inRQ, inACK, inTrans, throt, endInTrans, -- in com states
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inRQ, inACK, inTrans, inThrot,
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outRQ, outTrans, endOutTrans); -- out com states
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inThrotEnd, endInTrans, -- in com states
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outRQ, outTrans, outWait, endOutTrans); -- out com states
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signal pr_state, nx_state : t_fsmState;
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signal pr_state, nx_state : t_fsmState;
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-- XST specific synthesize attributes
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attribute safe_recovery_state of pr_state : signal is "idle";
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attribute safe_recovery_state of nx_state : signal is "idle";
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-- interconection signals
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-- interconection signals
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signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
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signal s_FIFOrst,
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s_RDYX,
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s_WRX : std_logic;
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-- USB to Xilinx (U2X)
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-- USB to Xilinx (U2X)
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signal s_U2X_WR_EN : std_logic;
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signal s_U2X_WR_EN : std_logic;
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-- Xilinx to USB (X2U)
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-- Xilinx to USB (X2U)
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signal s_X2U_RD_EN : std_logic;
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signal s_X2U_RD_EN : std_logic;
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begin
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begin
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o_FIFOrst <= s_FIFOrst;
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o_FIFOrst <= s_FIFOrst;
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o_X2U_RD_EN <= s_X2U_RD_EN;
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o_X2U_RD_EN <= s_X2U_RD_EN;
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o_WRX <= s_WRX;
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o_WRX <= s_WRX;
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o_RDYX <= s_RDYX;
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o_RDYX <= s_RDYX;
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o_U2X_WR_EN <= s_U2X_WR_EN;
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o_U2X_WR_EN <= s_U2X_WR_EN;
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o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
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o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
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o_ABORT <= s_ABORT;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- FSM GPIF
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-- FSM GPIF
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- state reg
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-- state reg
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action : process(i_IFCLK, i_nReset)
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action : process(i_IFCLK, i_nReset)
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variable v_setup : integer range 0 to 15;
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variable v_setup : integer range 0 to 15;
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begin
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begin
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if i_nReset = '0' then
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if i_nReset = '0' then
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pr_state <= rst;
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pr_state <= rst;
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v_setup := 0;
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elsif rising_edge(i_IFCLK) then
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elsif rising_edge(i_IFCLK) then
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if v_setup < SETUP_TIME then
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v_setup := v_setup + 1;
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elsif nx_state = rst then
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v_setup := 0;
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pr_state <= nx_state;
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else
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pr_state <= nx_state;
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pr_state <= nx_state;
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end if;
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end if;
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end if;
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end process action;
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end process action;
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-- comb logic
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-- comb logic
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transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_AM_FULL, i_X2U_EMPTY)
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transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_AM_FULL, i_X2U_EMPTY)
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begin -- process transaction
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begin -- process transaction
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-- default signal values to avoid latches:
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-- default signal values to avoid latches:
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s_FIFOrst <= '0';
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s_FIFOrst <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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nx_state <= idle;
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nx_state <= idle;
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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o_LEDrun <= '1';
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s_ABORT <= '0';
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o_LEDrx <= '0';
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o_RX <= '0';
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o_LEDtx <= '0';
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o_TX <= '0';
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case pr_state is
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case pr_state is
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-- controll
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-- controll
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when rst =>
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when rst =>
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-- output signal values:
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-- output signal values:
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s_FIFOrst <= '1';
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s_FIFOrst <= '1';
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_ABORT <= '1';
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o_RX <= '0';
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o_TX <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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else
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nx_state <= idle;
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nx_state <= idle;
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o_LEDrun <= '0';
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end if;
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when idle =>
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when idle =>
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-- output signal values:
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-- output signal values:
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s_FIFOrst <= '0';
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s_FIFOrst <= '0';
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_X2U_RD_EN <= '0';
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s_bus_trans_dir <= readFromGPIF;
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s_bus_trans_dir <= readFromGPIF;
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '1' and i_RDYU = '0' then
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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nx_state <= inRQ;
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elsif i_WRU = '0' and i_X2U_EMPTY = '0' then
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elsif i_WRU = '0' and i_X2U_EMPTY = '0' then
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nx_state <= outRQ;
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nx_state <= outRQ;
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else
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else
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nx_state <= idle;
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nx_state <= idle;
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end if;
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end if;
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-- in trans
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-- in trans
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when inRQ =>
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when inRQ =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_U2X_AM_FULL = '0' then
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elsif i_U2X_FULL = '0' then
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nx_state <= inACK;
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nx_state <= inACK;
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s_RDYX <= '1';
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else
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else
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nx_state <= idle;
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nx_state <= idle;
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end if;
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end if;
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when inACK =>
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when inACK =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '1';
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '1';
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o_RX <= '1';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '1' then
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elsif i_WRU = '1' then
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nx_state <= inTrans;
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nx_state <= inTrans;
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s_U2X_WR_EN <= '1';
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--nx_state <= inDummy;
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s_RDYX <= '1';
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else
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else
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nx_state <= endInTrans;
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nx_state <= endInTrans;
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end if;
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end if;
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when inTrans =>
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when inTrans =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '1';
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o_LEDrx <= '1';
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s_U2X_WR_EN <= '1';
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o_RX <= '1';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '0' then
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elsif i_WRU = '0' then
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nx_state <= endInTrans;
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nx_state <= endInTrans;
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s_RDYX <= '1';
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elsif i_U2X_FULL = '1' then
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s_U2X_WR_EN <= '1';
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nx_state <= inThrot;
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elsif i_U2X_AM_FULL = '1' then
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nx_state <= throt;
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s_U2X_WR_EN <= '1';
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else
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else
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nx_state <= inTrans;
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nx_state <= inTrans;
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s_RDYX <= '1';
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s_U2X_WR_EN <= '1';
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end if;
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end if;
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when throt =>
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when inThrot =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_U2X_WR_EN <= '0';
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s_U2X_WR_EN <= '0';
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o_RX <= '1';
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_U2X_AM_FULL = '0' then
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elsif i_U2X_FULL = '0' then
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--nx_state <= inThrotEnd;
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nx_state <= inACK;
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nx_state <= inACK;
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s_RDYX <= '1';
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s_U2X_WR_EN <= '1';
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elsif i_WRU = '0' then
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elsif i_WRU = '0' then
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nx_state <= endInTrans;
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nx_state <= endInTrans;
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else
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else
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nx_state <= throt;
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nx_state <= inThrot;
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end if;
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end if;
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|
|
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--when inThrotEnd =>
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-- -- this is a one clock delay to help the fx2 to see the RDYX signal.
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|
|
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-- -- output signal values:
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-- s_WRX <= '0';
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-- s_RDYX <= '1';
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-- s_U2X_WR_EN <= '0';
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-- o_RX <= '1';
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|
|
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-- -- state decisions
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-- nx_state <= inACK;
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|
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when endInTrans =>
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when endInTrans =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '0';
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s_WRX <= '0';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_U2X_WR_EN <= '1';
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s_U2X_WR_EN <= '1';
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|
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-- state decisions
|
-- state decisions
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nx_state <= idle;
|
nx_state <= idle;
|
|
|
|
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-- out trans
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-- out trans
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when outRQ =>
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when outRQ =>
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-- output signal values:
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-- output signal values:
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s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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|
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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s_WRX <= '0';
|
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elsif i_WRU = '1' and i_RDYU = '0' then
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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nx_state <= inRQ;
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elsif i_WRU = '0' and i_RDYU = '0' then -- vervollständigt, wenn ez-usb noch beschäfigt mit altem transfer
|
elsif i_WRU = '0' and i_RDYU = '0' then -- vervollständigt, wenn ez-usb noch beschäfigt mit altem transfer
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s_X2U_RD_EN <= '1';
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--s_X2U_RD_EN <= '1';
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nx_state <= outTrans;
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nx_state <= outTrans;
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-- s_bus_trans_dir <= writeToGPIF;
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-- s_bus_trans_dir <= writeToGPIF;
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else
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else
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nx_state <= outRQ;
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nx_state <= outRQ;
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end if;
|
end if;
|
|
|
|
|
when outTrans =>
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when outTrans =>
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-- output signal values:
|
-- output signal values:
|
s_WRX <= '1';
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s_WRX <= '1';
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s_RDYX <= '0';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '1';
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s_X2U_RD_EN <= '1';
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s_bus_trans_dir <= writeToGPIF;
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s_bus_trans_dir <= writeToGPIF;
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o_LEDtx <= '1';
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o_TX <= '1';
|
|
|
-- state decisions
|
-- state decisions
|
if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
|
nx_state <= rst;
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s_WRX <= '0';
|
|
s_X2U_RD_EN <= '0';
|
|
s_bus_trans_dir <= readFromGPIF;
|
|
elsif i_X2U_EMPTY = '1' then
|
elsif i_X2U_EMPTY = '1' then
|
nx_state <= endOutTrans;
|
nx_state <= endOutTrans;
|
elsif i_WRU = '0' and i_RDYU = '1' then
|
elsif i_WRU = '0' and i_RDYU = '1' then
|
nx_state <= outTrans;
|
nx_state <= outTrans;
|
else
|
else
|
s_X2U_RD_EN <= '0'; -- to realise a wait case
|
--s_X2U_RD_EN <= '0'; -- to realise a wait case
|
|
nx_state <= outWait;
|
|
end if;
|
|
|
|
when outWait =>
|
|
-- output signal values:
|
|
s_WRX <= '1';
|
|
s_RDYX <= '0';
|
|
s_X2U_RD_EN <= '0';
|
|
o_TX <= '1';
|
|
s_bus_trans_dir <= writeToGPIF;
|
|
|
|
-- state decisions
|
|
if i_WRU = '1' and i_RDYU = '1' then
|
|
nx_state <= rst;
|
|
elsif i_WRU = '0' and i_RDYU = '1' then
|
nx_state <= outTrans;
|
nx_state <= outTrans;
|
|
else
|
|
nx_state <= outWait;
|
end if;
|
end if;
|
|
|
when endOutTrans =>
|
when endOutTrans =>
|
-- output signal values:
|
-- output signal values:
|
s_RDYX <= '0';
|
s_RDYX <= '0';
|
s_WRX <= '1'; -- nötig um letzte 16bit an ez-usb zu schreiben
|
s_WRX <= '1'; -- nötig um letzte 16bit an ez-usb zu schreiben
|
s_X2U_RD_EN <= '1'; -- nötig da empyte flag schon beim ersten fifo zugriff auftaucht, zweite 16bit müssen noch gelesen werden
|
s_X2U_RD_EN <= '1'; -- nötig da empyte flag schon beim ersten fifo zugriff auftaucht, zweite 16bit müssen noch gelesen werden
|
s_bus_trans_dir <= writeToGPIF;
|
s_bus_trans_dir <= writeToGPIF;
|
|
|
-- state decisions
|
-- state decisions
|
nx_state <= idle;
|
nx_state <= idle;
|
|
|
-- error case
|
-- error case
|
when others =>
|
when others =>
|
nx_state <= idle;
|
nx_state <= idle;
|
end case;
|
end case;
|
|
|
end process transaction;
|
end process transaction;
|
|
|
end com_core;
|
end fsm;
|
|
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No newline at end of file
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No newline at end of file
|
