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https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk
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Rev 5 |
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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ENTITY TB_ALU IS
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ENTITY TB_ALU IS
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END TB_ALU;
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END TB_ALU;
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ARCHITECTURE behavior OF TB_ALU IS
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ARCHITECTURE behavior OF TB_ALU IS
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COMPONENT Alu
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COMPONENT Alu
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PORT(
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PORT(
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A : IN std_logic_vector(7 downto 0);
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A : IN std_logic_vector(7 downto 0);
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B : IN std_logic_vector(7 downto 0);
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B : IN std_logic_vector(7 downto 0);
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op : IN std_logic;
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op : IN std_logic;
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S : OUT std_logic_vector(7 downto 0)
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S : OUT std_logic_vector(7 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal A : std_logic_vector(7 downto 0) := (others => '0');
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signal A : std_logic_vector(7 downto 0) := (others => '0');
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signal B : std_logic_vector(7 downto 0) := (others => '0');
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signal B : std_logic_vector(7 downto 0) := (others => '0');
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signal op : std_logic := '0';
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signal op : std_logic := '0';
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--Outputs
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--Outputs
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signal S : std_logic_vector(7 downto 0);
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signal S : std_logic_vector(7 downto 0);
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BEGIN
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BEGIN
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uut: Alu PORT MAP (
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uut: Alu PORT MAP (
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A => A,
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A => A,
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B => B,
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B => B,
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op => op,
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op => op,
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S => S
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S => S
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);
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);
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A <= X"05" after 10 ns , X"0F" after 30 ns;
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A <= X"05" after 10 ns , X"0F" after 30 ns;
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B <= X"0A" after 10 ns , X"08" after 30 ns;
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B <= X"0A" after 10 ns , X"08" after 30 ns;
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op <= '1' after 20 ns , '0' after 40 ns;
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op <= '1' after 20 ns , '0' after 40 ns;
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END;
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END;
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