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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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ENTITY TB_Register IS
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ENTITY TB_Register IS
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END TB_Register;
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END TB_Register;
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ARCHITECTURE behavior OF TB_Register IS
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ARCHITECTURE behavior OF TB_Register IS
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COMPONENT Regeister
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COMPONENT Regeister
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PORT(
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PORT(
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clock : IN std_logic;
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clock : IN std_logic;
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enable : IN std_logic;
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enable : IN std_logic;
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reset : IN std_logic;
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reset : IN std_logic;
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din : IN std_logic_vector(7 downto 0);
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din : IN std_logic_vector(7 downto 0);
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dout : OUT std_logic_vector(7 downto 0)
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dout : OUT std_logic_vector(7 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal clock : std_logic := '0';
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signal clock : std_logic := '0';
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signal enable : std_logic := '0';
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signal enable : std_logic := '0';
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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signal din : std_logic_vector(7 downto 0) ;
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signal din : std_logic_vector(7 downto 0) ;
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signal dout : std_logic_vector(7 downto 0);
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signal dout : std_logic_vector(7 downto 0);
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: Regeister PORT MAP (
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uut: Regeister PORT MAP (
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clock => clock,
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clock => clock,
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enable => enable,
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enable => enable,
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reset => reset,
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reset => reset,
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din => din,
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din => din,
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dout => dout
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dout => dout
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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clock <= '0';
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clock <= '0';
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wait for clock_period/2;
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wait for clock_period/2;
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clock <= '1';
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clock <= '1';
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wait for clock_period/2;
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wait for clock_period/2;
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end process;
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end process;
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reset <= '1' after clock_period/2 ,'0' after clock_period*3/2;
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reset <= '1' after clock_period/2 ,'0' after clock_period*3/2;
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enable<= '1' after clock_period*2 ,'0' after clock_period*7;
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enable<= '1' after clock_period*2 ,'0' after clock_period*7;
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din <= X"05" after clock_period ,
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din <= X"05" after clock_period ,
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X"0A" after clock_period*2,
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X"0A" after clock_period*2,
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X"1A" after clock_period*3,
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X"1A" after clock_period*3,
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X"2A" after clock_period*4,
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X"2A" after clock_period*4,
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X"3A" after clock_period*5,
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X"3A" after clock_period*5,
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X"4A" after clock_period*6,
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X"4A" after clock_period*6,
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X"5A" after clock_period*7,
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X"5A" after clock_period*7,
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X"6B" after clock_period*8;
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X"6B" after clock_period*8;
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END;
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END;
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