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https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk
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Rev 6 |
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Adder is
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entity Adder is
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generic(
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size : integer:= 4
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);
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port(
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port(
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A : in std_logic_vector;
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A : in std_logic_vector(size-1 downto 0);
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B : in std_logic_vector;
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B : in std_logic_vector(size-1 downto 0);
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Cin : in std_logic;
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Cin : in std_logic;
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S : out std_logic_vector;
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S : out std_logic_vector(size-1 downto 0);
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Cout : out std_logic);
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Cout : out std_logic);
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end Adder;
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end Adder;
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architecture Behavioral of Adder is
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architecture Behavioral of Adder is
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component FullAdder is
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component FullAdder is
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port(
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port(
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A :in std_logic;
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A :in std_logic;
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B :in std_logic;
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B :in std_logic;
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Cin :in std_logic;
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Cin :in std_logic;
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Sum :out std_logic;
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Sum :out std_logic;
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Cout:out std_logic);
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Cout:out std_logic);
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end component;
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end component;
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signal carry : std_logic_vector(A'length downto 0);
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signal carry : std_logic_vector(A'length downto 0);
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begin
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begin
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carry(0) <= cin;
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carry(0) <= cin;
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cout <= carry(A'length);
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cout <= carry(A'length);
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AdderGen : for i in A'range generate
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AdderGen : for i in A'range generate
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FA : FullAdder port map(A(i),B(i),carry(i),S(i),carry(i+1));
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FA : FullAdder port map(A(i),B(i),carry(i),S(i),carry(i+1));
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end generate;
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end generate;
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end Behavioral;
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end Behavioral;
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