URL
https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 2 |
Rev 6 |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
|
entity counter is
|
entity counter is
|
|
generic(
|
|
size : integer:= 4
|
|
);
|
port(
|
port(
|
clock : in std_logic;
|
clock : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
value : out std_logic_vector);
|
value : out std_logic_vector(size-1 downto 0));
|
end counter;
|
end counter;
|
|
|
architecture behavioral of counter is
|
architecture behavioral of counter is
|
|
|
signal internal_value : std_logic_vector(value'range):= (others => '0');
|
signal internal_value : std_logic_vector(value'range):= (others => '0');
|
|
|
begin
|
begin
|
|
|
counter_proc:
|
counter_proc:
|
process(clock)
|
process(clock)
|
begin
|
begin
|
if (rising_edge(clock)) then
|
if (rising_edge(clock)) then
|
if (reset = '1') then
|
if (reset = '1') then
|
internal_value <= (others => '0');
|
internal_value <= (others => '0');
|
else
|
else
|
internal_value <= internal_value + '1';
|
internal_value <= internal_value + '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
value <= internal_value;
|
value <= internal_value;
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.