OpenCores
URL https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk

Subversion Repositories generic_booth_multipler

[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [00.Regeister.vhd] - Diff between revs 2 and 6

Only display areas with differences | Details | Blame | View Log

Rev 2 Rev 6
 
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity Regeister is
entity Regeister is
 
        generic (
 
                size: integer := 4
 
        );
        port(
        port(
                clock    :in    std_logic;
                clock :in       std_logic;
                enable :in      std_logic;
                enable :in      std_logic;
                reset    :in    std_logic;
                reset    :in    std_logic;
                din      :in    std_logic_vector;
                din      :in    std_logic_vector(size-1 downto 0);
                dout     :out std_logic_vector);
                dout :out std_logic_vector(size-1 downto 0));
end Regeister;
end Regeister;
 
 
architecture Behavioral of Regeister is
architecture Behavioral of Regeister is
        signal data :std_logic_vector(din'range):=(OTHERS=>'0');
        signal data :std_logic_vector(din'range):=(OTHERS=>'0');
begin
begin
        process(clock)
        process(clock)
        begin
        begin
                if(clock'event and clock='1')then
                if(clock'event and clock='1')then
                        if(reset ='1' )then
                        if(reset ='1' )then
                                data <=(others =>'0');
                                data <=(others =>'0');
                        elsif(enable = '1')then
                        elsif(enable = '1')then
                                data <= din;
                                data <= din;
                        else
                        else
                                data <= data;
                                data <= data;
                        end if;
                        end if;
                end if;
                end if;
        end process;
        end process;
        dout <= data;
        dout <= data;
 
 
end Behavioral;
end Behavioral;
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.