`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: UPT
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// Company: UPT
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// Engineer: Oana Boncalo & Alexandru Amaricai
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// Engineer: Oana Boncalo & Alexandru Amaricai
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//
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//
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// Create Date: 15:37:02 04/10/2013
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// Create Date: 15:37:02 04/10/2013
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// Design Name:
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// Design Name:
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// Module Name: debounceRst
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// Module Name: debounceRst
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module debounceRst(
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module debounceRst(
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input clk,
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input clk,
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input noisyRst,
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input noisyRst,
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input PLLLocked,
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input PLLLocked,
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output cleanPLLRst,
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output cleanPLLRst,
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output cleanAsyncRst
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output cleanAsyncRst
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);
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);
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localparam NR_SAMPLES = 10;
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localparam NR_SAMPLES = 10;
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localparam DELAY_CC = 100;
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localparam DELAY_CC = 100;
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localparam BITS_DELAY_CC = 8;// 8 = ceil(log2(DELAY_CC));
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localparam BITS_DELAY_CC = 8;// 8 = ceil(log2(DELAY_CC));
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reg [NR_SAMPLES-1: 0] rst_samples;
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reg [NR_SAMPLES-1: 0] rst_samples;
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wire rst_samples_and_N, rst_samples_and_N_1;
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wire rst_samples_and_N, rst_samples_and_N_1;
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reg [DELAY_CC-1: 0] rst_debounce_delay_loop = {1'b0, {(DELAY_CC-1){1'b1}}};
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reg [DELAY_CC-1: 0] rst_debounce_delay_loop = {1'b0, {(DELAY_CC-1){1'b1}}};
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reg [BITS_DELAY_CC-1: 0] rst_cnt_delay = 100 + 128;//100 + {1'b1, {(BITS_DELAY_CC-2){1'b0}}}; //keep reset active for DELAY_CC time
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reg [BITS_DELAY_CC-1: 0] rst_cnt_delay = 100 + 128;//100 + {1'b1, {(BITS_DELAY_CC-2){1'b0}}}; //keep reset active for DELAY_CC time
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wire async_rst, PLLRst, rst_edge, start_up_rst;
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wire async_rst, PLLRst, rst_edge, start_up_rst;
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// --4-bit Shift Register For resetting the DCM on startup (Xilinx Answer Record: 14425)
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// --4-bit Shift Register For resetting the PLL
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//--Asserts Start_Up_Rst for 4 clock periods
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//--Asserts Start_Up_Rst for 4 clock periods
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SRL16E #(
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SRL16E #(
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.INIT(16'h000F) // Initial Value of Shift Register
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.INIT(16'h000F) // Initial Value of Shift Register
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) SRL16E_inst (
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) SRL16E_inst (
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.Q(start_up_rst), // SRL data output
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.Q(start_up_rst), // SRL data output
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.A0 (1'b1), //-- Select[0] input
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.A0 (1'b1), //-- Select[0] input
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.A1 (1'b1), //-- Select[1] input
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.A1 (1'b1), //-- Select[1] input
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.A2 (1'b0), //-- Select[2] input
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.A2 (1'b0), //-- Select[2] input
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.A3 (1'b0), //-- Select[3] input
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.A3 (1'b0), //-- Select[3] input
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.CE (1'b1), // Clock enable input
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.CE (1'b1), // Clock enable input
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.CLK(clk), // Clock input
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.CLK(clk), // Clock input
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.D(1'b0) // SRL data input
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.D(1'b0) // SRL data input
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);
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);
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//debounce logic
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//debounce logic
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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rst_samples <= {rst_samples [NR_SAMPLES-2: 0],noisyRst};
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rst_samples <= {rst_samples [NR_SAMPLES-2: 0],noisyRst};
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end
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end
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assign rst_samples_and_N = & rst_samples;
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assign rst_samples_and_N = & rst_samples;
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assign rst_samples_and_N_1 = & rst_samples[NR_SAMPLES-2:0];
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assign rst_samples_and_N_1 = & rst_samples[NR_SAMPLES-2:0];
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//detect edge
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//detect edge
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assign rst_edge = (rst_samples_and_N_1 && (! rst_samples_and_N))? 1'b1: 1'b0;
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assign rst_edge = (rst_samples_and_N_1 && (! rst_samples_and_N))? 1'b1: 1'b0;
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//----------------------------------------------------------------------------------
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//----------------------------------------------------------------------------------
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//-- Reset with take-off and landing
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//-- Reset with take-off and landing
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//-- delay 95 cc = RST_SYNC_NUM - 4 reset
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//-- delay 95 cc = DELAY_CC - 4 reset
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//-- then keep it active for 3 cc (as long as one of RstQ(RST_SYNC_NUM-2), RstQ(RST_SYNC_NUM-3) or RstQ(RST_SYNC_NUM-4) is 0)
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//-- then keep it active for 3 cc (as long as one of rst_debounce_delay_loop[DELAY_CC-2], rst_debounce_delay_loop[DELAY_CC-3] or rst_debounce_delay_loop[DELAY_CC-4] is 0)
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//----------------------------------------------------------------------------------
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//----------------------------------------------------------------------------------
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (rst_edge || rst_debounce_delay_loop[DELAY_CC-1])
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if (rst_edge || rst_debounce_delay_loop[DELAY_CC-1])
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rst_debounce_delay_loop <= {rst_debounce_delay_loop[DELAY_CC-2:0],rst_debounce_delay_loop[DELAY_CC-1]};
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rst_debounce_delay_loop <= {rst_debounce_delay_loop[DELAY_CC-2:0],rst_debounce_delay_loop[DELAY_CC-1]};
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end
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end
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assign PLLRst = ((~rst_debounce_delay_loop[DELAY_CC-2]) || (~rst_debounce_delay_loop[DELAY_CC-3]) ||
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assign PLLRst = ((~rst_debounce_delay_loop[DELAY_CC-2]) || (~rst_debounce_delay_loop[DELAY_CC-3]) ||
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(~rst_debounce_delay_loop[DELAY_CC-4]) || start_up_rst)? 1'b1: 1'b0;
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(~rst_debounce_delay_loop[DELAY_CC-4]) || start_up_rst)? 1'b1: 1'b0;
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assign int_rst = ~PLLLocked;
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assign int_rst = ~PLLLocked;
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//decrement counter for 100 cc then RstD(RstD'high) becomes 0
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//decrement counter for 100 cc then rst_cnt_delay[BITS_DELAY_CC-1] becomes 0
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (int_rst)
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if (int_rst)
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rst_cnt_delay <= 228;//DELAY_CC + {1'b1, {(BITS_DELAY_CC-2){1'b0}}};//{1'b1, (BITS_DELAY_CC-1)'dDELAY_CC};
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rst_cnt_delay <= 228;//DELAY_CC + {1'b1, {(BITS_DELAY_CC-2){1'b0}}};
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else
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else
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if (rst_cnt_delay[BITS_DELAY_CC-1])
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if (rst_cnt_delay[BITS_DELAY_CC-1])
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rst_cnt_delay <= rst_cnt_delay - 1;
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rst_cnt_delay <= rst_cnt_delay - 1;
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end
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end
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assign async_rst = rst_cnt_delay[BITS_DELAY_CC-1] | rst_debounce_delay_loop[DELAY_CC -1]; //--100 cc have passed since reset signal has been generated
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assign async_rst = rst_cnt_delay[BITS_DELAY_CC-1] | rst_debounce_delay_loop[DELAY_CC -1]; //--100 cc have passed since reset signal has been generated
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assign cleanAsyncRst = async_rst;
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assign cleanAsyncRst = async_rst;
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assign cleanPLLRst = PLLRst;
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assign cleanPLLRst = PLLRst;
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endmodule
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endmodule
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