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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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-- Author: Andrzej Paluch
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-- Engineer:
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--
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--
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-- Create Date: 23:50:53 11/16/2011
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-- Create Date: 23:50:53 11/16/2011
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-- Design Name: MemoryBlock
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-- Design Name: MemoryBlock
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-- Module Name: J:/projekty/elektronika/USB_to_HPIB/usbToHpib/src/test/MemoryBlock_Test.vhd
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-- Module Name: J:/projekty/elektronika/USB_to_HPIB/usbToHpib/src/test/MemoryBlock_Test.vhd
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-- Project Name: usbToGpib
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-- Project Name: usbToGpib
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: MemoryBlock
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-- VHDL Test Bench Created by ISE for module: MemoryBlock
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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use work.helperComponents.all;
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use work.helperComponents.all;
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ENTITY MemoryBlock_Test_vhd IS
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ENTITY MemoryBlock_Test_vhd IS
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END MemoryBlock_Test_vhd;
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END MemoryBlock_Test_vhd;
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ARCHITECTURE behavior OF MemoryBlock_Test_vhd IS
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ARCHITECTURE behavior OF MemoryBlock_Test_vhd IS
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constant clk_period : time := 1us;
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constant clk_period : time := 1us;
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SIGNAL reset : std_logic := '0';
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SIGNAL reset : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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-------------------------------------------------
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-------------------------------------------------
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SIGNAL p1_addr : std_logic_vector(10 downto 0) := (others => '0');
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SIGNAL p1_addr : std_logic_vector(10 downto 0) := (others => '0');
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SIGNAL p1_data_in : std_logic_vector(7 downto 0) := (others => '0');
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SIGNAL p1_data_in : std_logic_vector(7 downto 0) := (others => '0');
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SIGNAL p1_data_out : std_logic_vector(7 downto 0);
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SIGNAL p1_data_out : std_logic_vector(7 downto 0);
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SIGNAL p1_strobe : std_logic := '0';
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SIGNAL p1_strobe : std_logic := '0';
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-------------------------------------------------
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-------------------------------------------------
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SIGNAL p2_addr : std_logic_vector(10 downto 0) := (others => '0');
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SIGNAL p2_addr : std_logic_vector(10 downto 0) := (others => '0');
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SIGNAL p2_data_in : std_logic_vector(7 downto 0) := (others => '0');
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SIGNAL p2_data_in : std_logic_vector(7 downto 0) := (others => '0');
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SIGNAL p2_data_out : std_logic_vector(7 downto 0);
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SIGNAL p2_data_out : std_logic_vector(7 downto 0);
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SIGNAL p2_strobe : std_logic := '0';
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SIGNAL p2_strobe : std_logic := '0';
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: MemoryBlock port map (
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uut: MemoryBlock port map (
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reset => reset,
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reset => reset,
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clk => clk,
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clk => clk,
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-------------------------------------------------
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-------------------------------------------------
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p1_addr => p1_addr,
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p1_addr => p1_addr,
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p1_data_in => p1_data_in,
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p1_data_in => p1_data_in,
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p1_strobe => p1_strobe,
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p1_strobe => p1_strobe,
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p1_data_out => p1_data_out,
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p1_data_out => p1_data_out,
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-------------------------------------------------
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-------------------------------------------------
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p2_addr => p2_addr,
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p2_addr => p2_addr,
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p2_data_in => p2_data_in,
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p2_data_in => p2_data_in,
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p2_strobe => p2_strobe,
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p2_strobe => p2_strobe,
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p2_data_out => p2_data_out
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p2_data_out => p2_data_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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stim_proc: PROCESS
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stim_proc: PROCESS
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BEGIN
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BEGIN
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reset <= '1';
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reset <= '1';
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wait for clk_period*4;
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wait for clk_period*4;
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reset <= '0';
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reset <= '0';
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wait for clk_period*20;
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wait for clk_period*20;
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p1_addr <= "00000000000";
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p1_addr <= "00000000000";
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p2_addr <= "00000000000";
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p2_addr <= "00000000000";
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p1_data_in <= "10101010";
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p1_data_in <= "10101010";
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wait for clk_period/2;
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wait for clk_period/2;
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p1_strobe <= '1';
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p1_strobe <= '1';
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wait for clk_period;
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wait for clk_period;
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p1_strobe <= '0';
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p1_strobe <= '0';
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wait for clk_period*4;
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wait for clk_period*4;
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p2_addr <= "00000000101";
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p2_addr <= "00000000101";
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p2_data_in <= "11010101";
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p2_data_in <= "11010101";
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wait for clk_period;
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wait for clk_period;
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p2_strobe <= '1';
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p2_strobe <= '1';
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wait for clk_period;
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wait for clk_period;
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p2_strobe <= '0';
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p2_strobe <= '0';
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wait for clk_period*4;
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wait for clk_period*4;
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p1_addr <= "00000000101";
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p1_addr <= "00000000101";
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wait; -- will wait forever
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wait; -- will wait forever
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END PROCESS;
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END PROCESS;
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END;
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END;
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