//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE GPIO Definitions ////
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//// WISHBONE GPIO Definitions ////
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//// ////
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//// ////
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//// This file is part of the GPIO project ////
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//// This file is part of the GPIO project ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// GPIO IP Definitions. ////
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//// GPIO IP Definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/10/02 18:54:35 simons
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// Revision 1.2 2003/10/02 18:54:35 simons
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// GPIO signals muxed with other peripherals, higland_board fixed.
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// GPIO signals muxed with other peripherals, higland_board fixed.
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//
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//
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// Revision 1.1.1.1 2003/06/24 09:09:23 simons
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// Revision 1.1.1.1 2003/06/24 09:09:23 simons
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// This files were moved here from toplevel folder.
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// This files were moved here from toplevel folder.
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//
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//
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// Revision 1.1.1.1 2003/06/11 18:51:13 simons
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// Revision 1.1.1.1 2003/06/11 18:51:13 simons
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// Initial import.
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// Initial import.
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//
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//
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// Revision 1.5 2002/11/11 21:36:28 lampret
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// Revision 1.5 2002/11/11 21:36:28 lampret
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// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
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// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
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//
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//
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// Revision 1.4 2002/05/06 18:25:31 lampret
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// Revision 1.4 2002/05/06 18:25:31 lampret
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// negedge flops are enabled by default.
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// negedge flops are enabled by default.
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//
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//
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// Revision 1.3 2001/12/25 17:12:35 lampret
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// Revision 1.3 2001/12/25 17:12:35 lampret
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// Added RGPIO_INTS.
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// Added RGPIO_INTS.
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//
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//
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// Revision 1.2 2001/11/15 02:24:37 lampret
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// Revision 1.2 2001/11/15 02:24:37 lampret
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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//
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//
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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//
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//
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// Revision 1.3 2001/07/15 00:21:10 lampret
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// Revision 1.3 2001/07/15 00:21:10 lampret
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// Registers can be omitted and will have certain default values
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// Registers can be omitted and will have certain default values
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//
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//
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// Revision 1.2 2001/07/14 20:39:26 lampret
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// Revision 1.2 2001/07/14 20:39:26 lampret
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// Better configurability.
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// Better configurability.
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//
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//
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// Revision 1.1 2001/06/05 07:45:26 lampret
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// Revision 1.1 2001/06/05 07:45:26 lampret
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// Added initial RTL and test benches. There are still some issues with these files.
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// Added initial RTL and test benches. There are still some issues with these files.
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//
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//
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//
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//
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|
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//
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//
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// Number of GPIO I/O signals
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// Number of GPIO I/O signals
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//
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//
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// This is the most important parameter of the GPIO IP core. It defines how many
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// This is the most important parameter of the GPIO IP core. It defines how many
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// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are
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// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are
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// required, use several instances of GPIO IP core.
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// required, use several instances of GPIO IP core.
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//
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//
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// Default is 16.
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// Default is 16.
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//
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//
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`define GPIO_IOS 31
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`define GPIO_IOS 31
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//
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//
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// Undefine this one if you don't want to remove GPIO block from your design
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// Undefine this one if you don't want to remove GPIO block from your design
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// but you also don't need it. When it is undefined, all GPIO ports still
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// but you also don't need it. When it is undefined, all GPIO ports still
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// remain valid and the core can be synthesized however internally there is
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// remain valid and the core can be synthesized however internally there is
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// no GPIO funationality.
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// no GPIO funationality.
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//
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//
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// Defined by default (duhh !).
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// Defined by default (duhh !).
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//
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//
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`define GPIO_IMPLEMENTED
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`define GPIO_IMPLEMENTED
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//
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//
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// Define to register all WISHBONE outputs.
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// Define to register all WISHBONE outputs.
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//
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//
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// Register outputs if you are using GPIO core as a block and synthesizing
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// Register outputs if you are using GPIO core as a block and synthesizing
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// and place&routing it separately from the rest of the system.
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// and place&routing it separately from the rest of the system.
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//
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//
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// If you do not need registered outputs, you can save some area by not defining
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// If you do not need registered outputs, you can save some area by not defining
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// this macro. By default it is defined.
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// this macro. By default it is defined.
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//
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//
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`define GPIO_REGISTERED_WB_OUTPUTS
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`define GPIO_REGISTERED_WB_OUTPUTS
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//
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//
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// Define to register all GPIO pad outputs.
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// Define to register all GPIO pad outputs.
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//
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//
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// Register outputs if you are using GPIO core as a block and synthesizing
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// Register outputs if you are using GPIO core as a block and synthesizing
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// and place&routing it separately from the rest of the system.
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// and place&routing it separately from the rest of the system.
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//
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//
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// If you do not need registered outputs, you can save some area by not defining
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// If you do not need registered outputs, you can save some area by not defining
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// this macro. By default it is defined.
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// this macro. By default it is defined.
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//
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//
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`define GPIO_REGISTERED_IO_OUTPUTS
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`define GPIO_REGISTERED_IO_OUTPUTS
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//
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//
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// Define to avoid using negative edge clock flip-flops for external clock
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// Define to avoid using negative edge clock flip-flops for external clock
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// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with
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// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with
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// positive edge clock flip-flops will be used.
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// positive edge clock flip-flops will be used.
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//
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//
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// By default it is not defined.
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// By default it is not defined.
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//
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//
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//`define GPIO_NO_NEGEDGE_FLOPS
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//`define GPIO_NO_NEGEDGE_FLOPS
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//
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//
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// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
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// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock
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// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
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// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on
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// clock signal, enable the following define.
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// clock signal, enable the following define.
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//
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//
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// By default it is not defined.
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// By default it is not defined.
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//
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//
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//`define GPIO_NO_CLKPAD_LOGIC
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//`define GPIO_NO_CLKPAD_LOGIC
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|
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//
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//
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// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
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// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
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// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
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// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
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// is usually useful if you want really small area (for example when implemented in
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// is usually useful if you want really small area (for example when implemented in
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// FPGA).
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// FPGA).
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//
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//
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// To follow GPIO IP core specification document this one must be defined. Also to
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// To follow GPIO IP core specification document this one must be defined. Also to
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// successfully run the test bench it must be defined. By default it is defined.
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// successfully run the test bench it must be defined. By default it is defined.
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//
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//
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`define GPIO_READREGS
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`define GPIO_READREGS
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//
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//
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// Full WISHBONE address decoding
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// Full WISHBONE address decoding
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//
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//
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// It is is undefined, partial WISHBONE address decoding is performed.
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// It is is undefined, partial WISHBONE address decoding is performed.
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// Undefine it if you need to save some area.
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// Undefine it if you need to save some area.
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//
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//
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// By default it is defined.
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// By default it is defined.
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//
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//
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`define GPIO_FULL_DECODE
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`define GPIO_FULL_DECODE
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//
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//
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// Strict 32-bit WISHBONE access
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// Strict 32-bit WISHBONE access
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//
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//
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// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
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// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
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// not defined, err_o is asserted whenever 8- or 16-bit access is made.
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// not defined, err_o is asserted whenever 8- or 16-bit access is made.
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// Undefine it if you need to save some area.
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// Undefine it if you need to save some area.
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//
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//
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// By default it is defined.
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// By default it is defined.
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//
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//
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//`define GPIO_STRICT_32BIT_ACCESS
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//`define GPIO_STRICT_32BIT_ACCESS
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//
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//
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`ifndef GPIO_STRICT_32BIT_ACCESS
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`ifndef GPIO_STRICT_32BIT_ACCESS
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// added by gorand :
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// added by gorand :
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// if GPIO_STRICT_32BIT_ACCESS is not defined,
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// if GPIO_STRICT_32BIT_ACCESS is not defined,
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// depending on number of gpio I/O lines, the following are defined :
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// depending on number of gpio I/O lines, the following are defined :
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// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined,
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// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined,
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// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,
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// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined,
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// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
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// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined,
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// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
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// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined,
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|
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`define GPIO_WB_BYTES4
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`define GPIO_WB_BYTES4
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`endif
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`endif
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//
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//
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// WISHBONE address bits used for full decoding of GPIO registers.
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// WISHBONE address bits used for full decoding of GPIO registers.
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//
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//
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`define GPIO_ADDRHH 6
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`define GPIO_ADDRHH 6
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`define GPIO_ADDRHL 5
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`define GPIO_ADDRHL 5
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`define GPIO_ADDRLH 1
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`define GPIO_ADDRLH 1
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`define GPIO_ADDRLL 0
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`define GPIO_ADDRLL 0
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|
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//
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//
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// Bits of WISHBONE address used for partial decoding of GPIO registers.
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// Bits of WISHBONE address used for partial decoding of GPIO registers.
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//
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//
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// Default 4:2.
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// Default 4:2.
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//
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//
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`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
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`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1
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|
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//
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//
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// Addresses of GPIO registers
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// Addresses of GPIO registers
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//
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//
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// To comply with GPIO IP core specification document they must go from
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// To comply with GPIO IP core specification document they must go from
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// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,
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// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT,
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// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL
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// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL
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//
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//
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// If particular register is not needed, it's address definition can be omitted
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// If particular register is not needed, it's address definition can be omitted
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// and the register will not be implemented. Instead a fixed default value will
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// and the register will not be implemented. Instead a fixed default value will
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// be used.
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// be used.
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//
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//
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`define GPIO_RGPIO_IN 3'h0 // Address 0x00
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`define GPIO_RGPIO_IN 3'h0 // Address 0x00
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`define GPIO_RGPIO_OUT 3'h1 // Address 0x04
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`define GPIO_RGPIO_OUT 3'h1 // Address 0x04
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`define GPIO_RGPIO_OE 3'h2 // Address 0x08
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`define GPIO_RGPIO_OE 3'h2 // Address 0x08
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`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c
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`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c
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`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
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`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
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`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
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`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
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`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
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`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
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`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c
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`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c
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//
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//
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// Default values for unimplemented GPIO registers
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// Default values for unimplemented GPIO registers
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//
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//
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`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0
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`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0
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|
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//
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//
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// RGPIO_CTRL bits
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// RGPIO_CTRL bits
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//
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//
|
// To comply with the GPIO IP core specification document they must go from
|
// To comply with the GPIO IP core specification document they must go from
|
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
|
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT
|
//
|
//
|
`define GPIO_RGPIO_CTRL_ECLK 0
|
`define GPIO_RGPIO_CTRL_ECLK 0
|
`define GPIO_RGPIO_CTRL_NEC 1
|
`define GPIO_RGPIO_CTRL_NEC 1
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`define GPIO_RGPIO_CTRL_INTE 2
|
`define GPIO_RGPIO_CTRL_INTE 2
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`define GPIO_RGPIO_CTRL_INTS 3
|
`define GPIO_RGPIO_CTRL_INTS 3
|
|
|