//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// WISHBONE General-Purpose I/O ////
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//// WISHBONE General-Purpose I/O ////
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//// ////
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//// ////
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//// This file is part of the GPIO project ////
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//// This file is part of the GPIO project ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implementation of GPIO IP core according to ////
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//// Implementation of GPIO IP core according to ////
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//// GPIO IP core specification document. ////
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//// GPIO IP core specification document. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/12/12 07:12:58 lampret
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// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
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//
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// Revision 1.3 2001/11/15 02:24:37 lampret
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// Revision 1.3 2001/11/15 02:24:37 lampret
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
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//
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//
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// Revision 1.2 2001/10/31 02:26:51 lampret
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// Revision 1.2 2001/10/31 02:26:51 lampret
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// Fixed wb_err_o.
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// Fixed wb_err_o.
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//
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//
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Revision 1.1 2001/09/18 18:49:07 lampret
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Revision 1.1 2001/08/21 21:39:28 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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//
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//
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// Revision 1.2 2001/07/14 20:39:26 lampret
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// Revision 1.2 2001/07/14 20:39:26 lampret
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// Better configurability.
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// Better configurability.
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//
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//
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// Revision 1.1 2001/06/05 07:45:26 lampret
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// Revision 1.1 2001/06/05 07:45:26 lampret
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// Added initial RTL and test benches. There are still some issues with these files.
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// Added initial RTL and test benches. There are still some issues with these files.
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "gpio_defines.v"
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`include "gpio_defines.v"
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module gpio_top(
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module gpio_top(
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// WISHBONE Interface
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// WISHBONE Interface
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wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
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wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
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wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
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wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
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// Auxiliary inputs interface
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// Auxiliary inputs interface
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aux_i,
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aux_i,
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// External GPIO Interface
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// External GPIO Interface
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in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
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in_pad_i, ext_clk_pad_i, out_pad_o, oen_padoen_o
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);
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);
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parameter dw = 32;
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parameter dw = 32;
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parameter aw = `GPIO_ADDRHH+1;
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parameter aw = `GPIO_ADDRHH+1;
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parameter gw = `GPIO_IOS;
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parameter gw = `GPIO_IOS;
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//
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//
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// WISHBONE Interface
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// WISHBONE Interface
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//
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//
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input wb_clk_i; // Clock
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input wb_clk_i; // Clock
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input wb_rst_i; // Reset
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input wb_rst_i; // Reset
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input wb_cyc_i; // cycle valid input
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input wb_cyc_i; // cycle valid input
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input [aw-1:0] wb_adr_i; // address bus inputs
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input [aw-1:0] wb_adr_i; // address bus inputs
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input [dw-1:0] wb_dat_i; // input data bus
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input [dw-1:0] wb_dat_i; // input data bus
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input [3:0] wb_sel_i; // byte select inputs
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input [3:0] wb_sel_i; // byte select inputs
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input wb_we_i; // indicates write transfer
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input wb_we_i; // indicates write transfer
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input wb_stb_i; // strobe input
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input wb_stb_i; // strobe input
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output [dw-1:0] wb_dat_o; // output data bus
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output [dw-1:0] wb_dat_o; // output data bus
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output wb_ack_o; // normal termination
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output wb_ack_o; // normal termination
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output wb_err_o; // termination w/ error
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output wb_err_o; // termination w/ error
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output wb_inta_o; // Interrupt request output
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output wb_inta_o; // Interrupt request output
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// Auxiliary Inputs Interface
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// Auxiliary Inputs Interface
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input [gw-1:0] aux_i; // Auxiliary inputs
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input [gw-1:0] aux_i; // Auxiliary inputs
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//
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//
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// External GPIO Interface
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// External GPIO Interface
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//
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//
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input [gw-1:0] in_pad_i; // GPIO Inputs
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input [gw-1:0] in_pad_i; // GPIO Inputs
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input ext_clk_pad_i; // GPIO Eclk
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input ext_clk_pad_i; // GPIO Eclk
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output [gw-1:0] out_pad_o; // GPIO Outputs
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output [gw-1:0] out_pad_o; // GPIO Outputs
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output [gw-1:0] oen_padoen_o; // GPIO output drivers enables
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output [gw-1:0] oen_padoen_o; // GPIO output drivers enables
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`ifdef GPIO_IMPLEMENTED
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`ifdef GPIO_IMPLEMENTED
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//
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//
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// GPIO Input Register (or no register)
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// GPIO Input Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_IN
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`ifdef GPIO_RGPIO_IN
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reg [gw-1:0] rgpio_in; // RGPIO_IN register
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reg [gw-1:0] rgpio_in; // RGPIO_IN register
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`else
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`else
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wire [gw-1:0] rgpio_in; // No register
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wire [gw-1:0] rgpio_in; // No register
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`endif
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`endif
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//
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//
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// GPIO Output Register (or no register)
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// GPIO Output Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_OUT
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`ifdef GPIO_RGPIO_OUT
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reg [gw-1:0] rgpio_out; // RGPIO_OUT register
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reg [gw-1:0] rgpio_out; // RGPIO_OUT register
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`else
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`else
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wire [gw-1:0] rgpio_out; // No register
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wire [gw-1:0] rgpio_out; // No register
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`endif
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`endif
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//
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//
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// GPIO Output Driver Enable Register (or no register)
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// GPIO Output Driver Enable Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_OE
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`ifdef GPIO_RGPIO_OE
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reg [gw-1:0] rgpio_oe; // RGPIO_OE register
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reg [gw-1:0] rgpio_oe; // RGPIO_OE register
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`else
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`else
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wire [gw-1:0] rgpio_oe; // No register
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wire [gw-1:0] rgpio_oe; // No register
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`endif
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`endif
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//
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//
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// GPIO Interrupt Enable Register (or no register)
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// GPIO Interrupt Enable Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_INTE
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`ifdef GPIO_RGPIO_INTE
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reg [gw-1:0] rgpio_inte; // RGPIO_INTE register
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reg [gw-1:0] rgpio_inte; // RGPIO_INTE register
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`else
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`else
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wire [gw-1:0] rgpio_inte; // No register
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wire [gw-1:0] rgpio_inte; // No register
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`endif
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`endif
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//
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//
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// GPIO Positive edge Triggered Register (or no register)
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// GPIO Positive edge Triggered Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_PTRIG
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`ifdef GPIO_RGPIO_PTRIG
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reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register
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reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register
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`else
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`else
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wire [gw-1:0] rgpio_ptrig; // No register
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wire [gw-1:0] rgpio_ptrig; // No register
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`endif
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`endif
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//
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//
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// GPIO Auxiliary select Register (or no register)
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// GPIO Auxiliary select Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_AUX
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`ifdef GPIO_RGPIO_AUX
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reg [gw-1:0] rgpio_aux; // RGPIO_AUX register
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reg [gw-1:0] rgpio_aux; // RGPIO_AUX register
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`else
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`else
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wire [gw-1:0] rgpio_aux; // No register
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wire [gw-1:0] rgpio_aux; // No register
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`endif
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`endif
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//
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//
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// GPIO Control Register (or no register)
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// GPIO Control Register (or no register)
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//
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//
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`ifdef GPIO_RGPIO_CTRL
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`ifdef GPIO_RGPIO_CTRL
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reg [3:0] rgpio_ctrl; // RGPIO_CTRL register
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reg [3:0] rgpio_ctrl; // RGPIO_CTRL register
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`else
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`else
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wire [3:0] rgpio_ctrl; // No register
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wire [3:0] rgpio_ctrl; // No register
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`endif
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`endif
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//
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//
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// Internal wires & regs
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// Internal wires & regs
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//
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//
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wire rgpio_in_sel; // RGPIO_IN select
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wire rgpio_out_sel; // RGPIO_OUT select
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wire rgpio_out_sel; // RGPIO_OUT select
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wire rgpio_oe_sel; // RGPIO_OE select
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wire rgpio_oe_sel; // RGPIO_OE select
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wire rgpio_inte_sel; // RGPIO_INTE select
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wire rgpio_inte_sel; // RGPIO_INTE select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_ptrig_sel;// RGPIO_PTRIG select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_aux_sel; // RGPIO_AUX select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire rgpio_ctrl_sel; // RGPIO_CTRL select
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wire latch_clk; // Latch clock
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wire latch_clk; // Latch clock
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wire full_decoding; // Full address decoding qualification
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wire full_decoding; // Full address decoding qualification
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire [gw-1:0] in_muxed; // Muxed inputs
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wire wb_ack; // WB Acknowledge
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wire wb_ack; // WB Acknowledge
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wire wb_err; // WB Error
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wire wb_err; // WB Error
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wire wb_inta; // WB Interrupt
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wire wb_inta; // WB Interrupt
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reg [dw-1:0] wb_dat; // WB Data out
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reg [dw-1:0] wb_dat; // WB Data out
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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reg wb_ack_o; // WB Acknowledge
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reg wb_ack_o; // WB Acknowledge
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reg wb_err_o; // WB Error
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reg wb_err_o; // WB Error
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reg wb_inta_o; // WB Interrupt
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reg wb_inta_o; // WB Interrupt
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reg [dw-1:0] wb_dat_o; // WB Data out
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reg [dw-1:0] wb_dat_o; // WB Data out
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`endif
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`endif
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wire [gw-1:0] out_pad; // GPIO Outputs
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wire [gw-1:0] out_pad; // GPIO Outputs
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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`ifdef GPIO_REGISTERED_IO_OUTPUTS
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reg [gw-1:0] out_pad_o; // GPIO Outputs
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reg [gw-1:0] out_pad_o; // GPIO Outputs
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`endif
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`endif
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wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
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wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
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wire pext_clk; // External clock for posedge flops
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wire pext_clk; // External clock for posedge flops
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reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
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reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`ifdef GPIO_NO_NEGEDGE_FLOPS
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`else
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`else
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reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
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reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
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`endif
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`endif
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//
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//
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// All WISHBONE transfer terminations are successful except when:
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// All WISHBONE transfer terminations are successful except when:
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// a) full address decoding is enabled and address doesn't match
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// a) full address decoding is enabled and address doesn't match
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// any of the GPIO registers
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// any of the GPIO registers
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// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
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// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
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//
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//
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|
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//
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//
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// WB Acknowledge
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// WB Acknowledge
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//
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//
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assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
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assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
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|
|
//
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//
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// Optional registration of WB Ack
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// Optional registration of WB Ack
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//
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//
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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`ifdef GPIO_REGISTERED_WB_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_ack_o <= #1 1'b0;
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wb_ack_o <= #1 1'b0;
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else
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else
|
wb_ack_o <= #1 wb_ack;
|
wb_ack_o <= #1 wb_ack;
|
`else
|
`else
|
assign wb_ack_o = wb_ack;
|
assign wb_ack_o = wb_ack;
|
`endif
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`endif
|
|
|
//
|
//
|
// WB Error
|
// WB Error
|
//
|
//
|
`ifdef GPIO_FULL_DECODE
|
`ifdef GPIO_FULL_DECODE
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
|
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
|
`else
|
`else
|
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
|
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
|
`endif
|
`endif
|
`else
|
`else
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
`ifdef GPIO_STRICT_32BIT_ACCESS
|
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
|
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
|
`else
|
`else
|
assign wb_err = 1'b0;
|
assign wb_err = 1'b0;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
//
|
//
|
// Optional registration of WB error
|
// Optional registration of WB error
|
//
|
//
|
`ifdef GPIO_REGISTERED_WB_OUTPUTS
|
`ifdef GPIO_REGISTERED_WB_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_err_o <= #1 1'b0;
|
wb_err_o <= #1 1'b0;
|
else
|
else
|
wb_err_o <= #1 wb_err;
|
wb_err_o <= #1 wb_err;
|
`else
|
`else
|
assign wb_err_o = wb_err;
|
assign wb_err_o = wb_err;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Full address decoder
|
// Full address decoder
|
//
|
//
|
`ifdef GPIO_FULL_DECODE
|
`ifdef GPIO_FULL_DECODE
|
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
|
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
|
(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
|
(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
|
`else
|
`else
|
assign full_decoding = 1'b1;
|
assign full_decoding = 1'b1;
|
`endif
|
`endif
|
|
|
//
|
//
|
// GPIO registers address decoder
|
// GPIO registers address decoder
|
//
|
//
|
assign rgpio_in_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_IN) & full_decoding;
|
|
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
|
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
|
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
|
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
|
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
|
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
|
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
|
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
|
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
|
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
|
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
|
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
|
|
|
//
|
//
|
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
|
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
|
//
|
//
|
`ifdef GPIO_RGPIO_CTRL
|
`ifdef GPIO_RGPIO_CTRL
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_ctrl <= #1 4'b0;
|
rgpio_ctrl <= #1 4'b0;
|
else if (rgpio_ctrl_sel && wb_we_i)
|
else if (rgpio_ctrl_sel && wb_we_i)
|
rgpio_ctrl <= #1 wb_dat_i[3:0];
|
rgpio_ctrl <= #1 wb_dat_i[3:0];
|
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
|
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
|
rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] | wb_inta_o;
|
rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] | wb_inta_o;
|
`else
|
`else
|
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
|
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to RGPIO_OUT
|
// Write to RGPIO_OUT
|
//
|
//
|
`ifdef GPIO_RGPIO_OUT
|
`ifdef GPIO_RGPIO_OUT
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_out <= #1 {gw{1'b0}};
|
rgpio_out <= #1 {gw{1'b0}};
|
else if (rgpio_out_sel && wb_we_i)
|
else if (rgpio_out_sel && wb_we_i)
|
rgpio_out <= #1 wb_dat_i[gw-1:0];
|
rgpio_out <= #1 wb_dat_i[gw-1:0];
|
`else
|
`else
|
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
|
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
|
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
|
//
|
//
|
`ifdef GPIO_RGPIO_OE
|
`ifdef GPIO_RGPIO_OE
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_oe <= #1 {gw{1'b0}};
|
rgpio_oe <= #1 {gw{1'b0}};
|
else if (rgpio_oe_sel && wb_we_i)
|
else if (rgpio_oe_sel && wb_we_i)
|
rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
|
rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
|
`else
|
`else
|
assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
|
assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to RGPIO_INTE
|
// Write to RGPIO_INTE
|
//
|
//
|
`ifdef GPIO_RGPIO_INTE
|
`ifdef GPIO_RGPIO_INTE
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_inte <= #1 {gw{1'b0}};
|
rgpio_inte <= #1 {gw{1'b0}};
|
else if (rgpio_inte_sel && wb_we_i)
|
else if (rgpio_inte_sel && wb_we_i)
|
rgpio_inte <= #1 wb_dat_i[gw-1:0];
|
rgpio_inte <= #1 wb_dat_i[gw-1:0];
|
`else
|
`else
|
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
|
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to RGPIO_PTRIG
|
// Write to RGPIO_PTRIG
|
//
|
//
|
`ifdef GPIO_RGPIO_PTRIG
|
`ifdef GPIO_RGPIO_PTRIG
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_ptrig <= #1 {gw{1'b0}};
|
rgpio_ptrig <= #1 {gw{1'b0}};
|
else if (rgpio_ptrig_sel && wb_we_i)
|
else if (rgpio_ptrig_sel && wb_we_i)
|
rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
|
rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
|
`else
|
`else
|
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
|
assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to RGPIO_AUX
|
// Write to RGPIO_AUX
|
//
|
//
|
`ifdef GPIO_RGPIO_AUX
|
`ifdef GPIO_RGPIO_AUX
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_aux <= #1 {gw{1'b0}};
|
rgpio_aux <= #1 {gw{1'b0}};
|
else if (rgpio_aux_sel && wb_we_i)
|
else if (rgpio_aux_sel && wb_we_i)
|
rgpio_aux <= #1 wb_dat_i[gw-1:0];
|
rgpio_aux <= #1 wb_dat_i[gw-1:0];
|
`else
|
`else
|
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
|
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
|
`endif
|
`endif
|
|
|
//
|
//
|
// Latch into RGPIO_IN
|
// Latch into RGPIO_IN
|
//
|
//
|
`ifdef GPIO_RGPIO_IN
|
`ifdef GPIO_RGPIO_IN
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
rgpio_in <= #1 {gw{1'b0}};
|
rgpio_in <= #1 {gw{1'b0}};
|
else
|
else
|
rgpio_in <= #1 in_muxed;
|
rgpio_in <= #1 in_muxed;
|
`else
|
`else
|
assign rgpio_in = in_muxed;
|
assign rgpio_in = in_muxed;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Mux inputs directly from input pads with inputs sampled by external clock
|
// Mux inputs directly from input pads with inputs sampled by external clock
|
//
|
//
|
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
|
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
|
|
|
//
|
//
|
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
|
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
|
// If negedge flops are allowed, pext_clk only clocks posedge flops.
|
// If negedge flops are allowed, pext_clk only clocks posedge flops.
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
|
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
|
`else
|
`else
|
assign pext_clk = ext_clk_pad_i;
|
assign pext_clk = ext_clk_pad_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
|
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
assign extc_in = pextc_sampled;
|
assign extc_in = pextc_sampled;
|
`else
|
`else
|
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
|
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Latch using posedge external clock
|
// Latch using posedge external clock
|
//
|
//
|
always @(posedge pext_clk or posedge wb_rst_i)
|
always @(posedge pext_clk or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
pextc_sampled <= #1 {gw{1'b0}};
|
pextc_sampled <= #1 {gw{1'b0}};
|
else
|
else
|
pextc_sampled <= #1 in_pad_i;
|
pextc_sampled <= #1 in_pad_i;
|
|
|
//
|
//
|
// Latch using negedge external clock
|
// Latch using negedge external clock
|
//
|
//
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`ifdef GPIO_NO_NEGEDGE_FLOPS
|
`else
|
`else
|
always @(negedge ext_clk_pad_i or posedge wb_rst_i)
|
always @(negedge ext_clk_pad_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
nextc_sampled <= #1 {gw{1'b0}};
|
nextc_sampled <= #1 {gw{1'b0}};
|
else
|
else
|
nextc_sampled <= #1 in_pad_i;
|
nextc_sampled <= #1 in_pad_i;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Mux all registers when doing a read of GPIO registers
|
// Mux all registers when doing a read of GPIO registers
|
//
|
//
|
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
|
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
|
rgpio_ptrig or rgpio_aux or rgpio_ctrl)
|
rgpio_ptrig or rgpio_aux or rgpio_ctrl)
|
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
|
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
|
`ifdef GPIO_READREGS
|
`ifdef GPIO_READREGS
|
`GPIO_RGPIO_OUT: begin
|
`GPIO_RGPIO_OUT: begin
|
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
|
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};
|
end
|
end
|
`GPIO_RGPIO_OE: begin
|
`GPIO_RGPIO_OE: begin
|
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, ~rgpio_oe};
|
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};
|
end
|
end
|
`GPIO_RGPIO_INTE: begin
|
`GPIO_RGPIO_INTE: begin
|
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
|
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};
|
end
|
end
|
`GPIO_RGPIO_PTRIG: begin
|
`GPIO_RGPIO_PTRIG: begin
|
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
|
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};
|
end
|
end
|
`GPIO_RGPIO_AUX: begin
|
`GPIO_RGPIO_AUX: begin
|
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
|
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};
|
end
|
end
|
`GPIO_RGPIO_CTRL: begin
|
`GPIO_RGPIO_CTRL: begin
|
wb_dat[3:0] <= rgpio_ctrl;
|
wb_dat[3:0] = rgpio_ctrl;
|
wb_dat[dw-1:4] <= {dw-4{1'b0}};
|
wb_dat[dw-1:4] = {dw-4{1'b0}};
|
end
|
end
|
`endif
|
`endif
|
default: begin
|
default: begin
|
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
|
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
|
end
|
end
|
endcase
|
endcase
|
|
|
//
|
//
|
// WB data output
|
// WB data output
|
//
|
//
|
`ifdef GPIO_REGISTERED_WB_OUTPUTS
|
`ifdef GPIO_REGISTERED_WB_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_dat_o <= #1 {dw{1'b0}};
|
wb_dat_o <= #1 {dw{1'b0}};
|
else
|
else
|
wb_dat_o <= #1 wb_dat;
|
wb_dat_o <= #1 wb_dat;
|
`else
|
`else
|
assign wb_dat_o = wb_dat;
|
assign wb_dat_o = wb_dat;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Generate interrupt request
|
// Generate interrupt request
|
//
|
//
|
assign wb_inta = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
|
assign wb_inta = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
|
|
|
//
|
//
|
// Optional registration of WB interrupt
|
// Optional registration of WB interrupt
|
//
|
//
|
`ifdef GPIO_REGISTERED_WB_OUTPUTS
|
`ifdef GPIO_REGISTERED_WB_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
wb_inta_o <= #1 1'b0;
|
wb_inta_o <= #1 1'b0;
|
else
|
else
|
wb_inta_o <= #1 wb_inta;
|
wb_inta_o <= #1 wb_inta;
|
`else
|
`else
|
assign wb_inta_o = wb_inta;
|
assign wb_inta_o = wb_inta;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Output enables are RGPIO_OE bits
|
// Output enables are RGPIO_OE bits
|
//
|
//
|
assign oen_padoen_o = rgpio_oe;
|
assign oen_padoen_o = rgpio_oe;
|
|
|
//
|
//
|
// Generate GPIO outputs
|
// Generate GPIO outputs
|
//
|
//
|
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
|
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
|
|
|
//
|
//
|
// Optional registration of GPIO outputs
|
// Optional registration of GPIO outputs
|
//
|
//
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
`ifdef GPIO_REGISTERED_IO_OUTPUTS
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
if (wb_rst_i)
|
if (wb_rst_i)
|
out_pad_o <= #1 {gw{1'b0}};
|
out_pad_o <= #1 {gw{1'b0}};
|
else
|
else
|
out_pad_o <= #1 out_pad;
|
out_pad_o <= #1 out_pad;
|
`else
|
`else
|
assign out_pad_o = out_pad;
|
assign out_pad_o = out_pad;
|
`endif
|
`endif
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
|
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
|
// is cleared and WISHBONE transfers complete with errors
|
// is cleared and WISHBONE transfers complete with errors
|
//
|
//
|
assign wb_inta_o = 1'b0;
|
assign wb_inta_o = 1'b0;
|
assign wb_ack_o = 1'b0;
|
assign wb_ack_o = 1'b0;
|
assign wb_err_o = wb_cyc_i & wb_stb_i;
|
assign wb_err_o = wb_cyc_i & wb_stb_i;
|
assign oen_padoen_o = {gw{1'b1}};
|
assign oen_padoen_o = {gw{1'b1}};
|
assign out_pad_o = {gw{1'b0}};
|
assign out_pad_o = {gw{1'b0}};
|
|
|
//
|
//
|
// Read GPIO registers
|
// Read GPIO registers
|
//
|
//
|
assign wb_dat_o = {dw{1'b0}};
|
assign wb_dat_o = {dw{1'b0}};
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
