OpenCores

Rev 46	Rev 65
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// WISHBONE General-Purpose I/O ////`	`//// WISHBONE General-Purpose I/O ////`
`//// ////`	`//// ////`
`//// This file is part of the GPIO project ////`	`//// This file is part of the GPIO project ////`
`//// http://www.opencores.org/cores/gpio/ ////`	`//// http://www.opencores.org/cores/gpio/ ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// Implementation of GPIO IP core according to ////`	`//// Implementation of GPIO IP core according to ////`
`//// GPIO IP core specification document. ////`	`//// GPIO IP core specification document. ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
`//// Nothing ////`	`//// Nothing ////`
`//// ////`	`//// ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Damjan Lampret, lampret@opencores.org ////`	`//// - Damjan Lampret, lampret@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
`//// removed from the file and that any derivative work contains ////`	`//// removed from the file and that any derivative work contains ////`
`//// the original copyright notice and the associated disclaimer. ////`	`//// the original copyright notice and the associated disclaimer. ////`
`//// ////`	`//// ////`
`//// This source file is free software; you can redistribute it ////`	`//// This source file is free software; you can redistribute it ////`
`//// and/or modify it under the terms of the GNU Lesser General ////`	`//// and/or modify it under the terms of the GNU Lesser General ////`
`//// Public License as published by the Free Software Foundation; ////`	`//// Public License as published by the Free Software Foundation; ////`
`//// either version 2.1 of the License, or (at your option) any ////`	`//// either version 2.1 of the License, or (at your option) any ////`
`//// later version. ////`	`//// later version. ////`
`//// ////`	`//// ////`
`//// This source is distributed in the hope that it will be ////`	`//// This source is distributed in the hope that it will be ////`
`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`	`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`	`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
`//// PURPOSE. See the GNU Lesser General Public License for more ////`	`//// PURPOSE. See the GNU Lesser General Public License for more ////`
`//// details. ////`	`//// details. ////`
`//// ////`	`//// ////`
`//// You should have received a copy of the GNU Lesser General ////`	`//// You should have received a copy of the GNU Lesser General ////`
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
`// Revision 1.14 2003/11/06 13:59:07 gorand`	`// Revision 1.14 2003/11/06 13:59:07 gorand`
`// added support for 8-bit access to registers.`	`// added support for 8-bit access to registers.`
`//`	`//`
`// Revision 1.13 2002/11/18 22:35:18 lampret`	`// Revision 1.13 2002/11/18 22:35:18 lampret`
`// Bug fix. Interrupts were also asserted when condition was not met.`	`// Bug fix. Interrupts were also asserted when condition was not met.`
`//`	`//`
`// Revision 1.12 2002/11/11 21:36:28 lampret`	`// Revision 1.12 2002/11/11 21:36:28 lampret`
`// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].`	`// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].`
`//`	`//`
`// Revision 1.11 2002/03/13 20:56:28 lampret`	`// Revision 1.11 2002/03/13 20:56:28 lampret`
`// Removed zero padding as per Avi Shamli suggestion.`	`// Removed zero padding as per Avi Shamli suggestion.`
`//`	`//`
`// Revision 1.10 2002/03/13 20:47:57 lampret`	`// Revision 1.10 2002/03/13 20:47:57 lampret`
`// Ports changed per Ran Aviram suggestions.`	`// Ports changed per Ran Aviram suggestions.`
`//`	`//`
`// Revision 1.9 2002/03/09 03:43:27 lampret`	`// Revision 1.9 2002/03/09 03:43:27 lampret`
`// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)`	`// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)`
`//`	`//`
`// Revision 1.8 2002/01/14 19:06:28 lampret`	`// Revision 1.8 2002/01/14 19:06:28 lampret`
`// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.`	`// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.`
`//`	`//`
`// Revision 1.7 2001/12/25 17:21:21 lampret`	`// Revision 1.7 2001/12/25 17:21:21 lampret`
`// Fixed two typos.`	`// Fixed two typos.`
`//`	`//`
`// Revision 1.6 2001/12/25 17:12:35 lampret`	`// Revision 1.6 2001/12/25 17:12:35 lampret`
`// Added RGPIO_INTS.`	`// Added RGPIO_INTS.`
`//`	`//`
`// Revision 1.5 2001/12/12 20:35:53 lampret`	`// Revision 1.5 2001/12/12 20:35:53 lampret`
`// Fixing style.`	`// Fixing style.`
`//`	`//`
`// Revision 1.4 2001/12/12 07:12:58 lampret`	`// Revision 1.4 2001/12/12 07:12:58 lampret`
`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`	`// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)`
`//`	`//`
`// Revision 1.3 2001/11/15 02:24:37 lampret`	`// Revision 1.3 2001/11/15 02:24:37 lampret`
`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`	`// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.`
`//`	`//`
`// Revision 1.2 2001/10/31 02:26:51 lampret`	`// Revision 1.2 2001/10/31 02:26:51 lampret`
`// Fixed wb_err_o.`	`// Fixed wb_err_o.`
`//`	`//`
`// Revision 1.1 2001/09/18 18:49:07 lampret`	`// Revision 1.1 2001/09/18 18:49:07 lampret`
`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`	`// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.`
`//`	`//`
`// Revision 1.1 2001/08/21 21:39:28 lampret`	`// Revision 1.1 2001/08/21 21:39:28 lampret`
`// Changed directory structure, port names and drfines.`	`// Changed directory structure, port names and drfines.`
`//`	`//`
`// Revision 1.2 2001/07/14 20:39:26 lampret`	`// Revision 1.2 2001/07/14 20:39:26 lampret`
`// Better configurability.`	`// Better configurability.`
`//`	`//`
`// Revision 1.1 2001/06/05 07:45:26 lampret`	`// Revision 1.1 2001/06/05 07:45:26 lampret`
`// Added initial RTL and test benches. There are still some issues with these files.`	`// Added initial RTL and test benches. There are still some issues with these files.`
`//`	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
`include "gpio_defines.v"	`include "gpio_defines.v"

`module gpio_top(`	`module gpio_top(`
`// WISHBONE Interface`	`// WISHBONE Interface`
`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`	`wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,`
`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`	`wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,`

`// Auxiliary inputs interface`	`// Auxiliary inputs interface`
`aux_i,`	`aux_i,`

`// External GPIO Interface`	`// External GPIO Interface`
`ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o`	`ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o`
`);`	`);`

`parameter dw = 32;`	`parameter dw = 32;`
parameter aw = `GPIO_ADDRHH+1;	parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;	parameter gw = `GPIO_IOS;
`//`	`//`
`// WISHBONE Interface`	`// WISHBONE Interface`
`//`	`//`
`input wb_clk_i; // Clock`	`input wb_clk_i; // Clock`
`input wb_rst_i; // Reset`	`input wb_rst_i; // Reset`
`input wb_cyc_i; // cycle valid input`	`input wb_cyc_i; // cycle valid input`
`input [aw-1:0] wb_adr_i; // address bus inputs`	`input [aw-1:0] wb_adr_i; // address bus inputs`
`input [dw-1:0] wb_dat_i; // input data bus`	`input [dw-1:0] wb_dat_i; // input data bus`
`input [3:0] wb_sel_i; // byte select inputs`	`input [3:0] wb_sel_i; // byte select inputs`
`input wb_we_i; // indicates write transfer`	`input wb_we_i; // indicates write transfer`
`input wb_stb_i; // strobe input`	`input wb_stb_i; // strobe input`
`output [dw-1:0] wb_dat_o; // output data bus`	`output [dw-1:0] wb_dat_o; // output data bus`
`output wb_ack_o; // normal termination`	`output wb_ack_o; // normal termination`
`output wb_err_o; // termination w/ error`	`output wb_err_o; // termination w/ error`
`output wb_inta_o; // Interrupt request output`	`output wb_inta_o; // Interrupt request output`

`// Auxiliary Inputs Interface`	`// Auxiliary Inputs Interface`
`input [gw-1:0] aux_i; // Auxiliary inputs`	`input [gw-1:0] aux_i; // Auxiliary inputs`

`//`	`//`
`// External GPIO Interface`	`// External GPIO Interface`
`//`	`//`
`input [gw-1:0] ext_pad_i; // GPIO Inputs`	`input [gw-1:0] ext_pad_i; // GPIO Inputs`
`input clk_pad_i; // GPIO Eclk`	`input clk_pad_i; // GPIO Eclk`
`output [gw-1:0] ext_pad_o; // GPIO Outputs`	`output [gw-1:0] ext_pad_o; // GPIO Outputs`
`output [gw-1:0] ext_padoen_o; // GPIO output drivers enables`	`output [gw-1:0] ext_padoen_o; // GPIO output drivers enables`

`ifdef GPIO_IMPLEMENTED	`ifdef GPIO_IMPLEMENTED

`//`	`//`
`// GPIO Input Register (or no register)`	`// GPIO Input Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_IN	`ifdef GPIO_RGPIO_IN
`reg [gw-1:0] rgpio_in; // RGPIO_IN register`	`reg [gw-1:0] rgpio_in; // RGPIO_IN register`
`else	`else
`wire [gw-1:0] rgpio_in; // No register`	`wire [gw-1:0] rgpio_in; // No register`
`endif	`endif

`//`	`//`
`// GPIO Output Register (or no register)`	`// GPIO Output Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_OUT	`ifdef GPIO_RGPIO_OUT
`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`	`reg [gw-1:0] rgpio_out; // RGPIO_OUT register`
`else	`else
`wire [gw-1:0] rgpio_out; // No register`	`wire [gw-1:0] rgpio_out; // No register`
`endif	`endif

`//`	`//`
`// GPIO Output Driver Enable Register (or no register)`	`// GPIO Output Driver Enable Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_OE	`ifdef GPIO_RGPIO_OE
`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`	`reg [gw-1:0] rgpio_oe; // RGPIO_OE register`
`else	`else
`wire [gw-1:0] rgpio_oe; // No register`	`wire [gw-1:0] rgpio_oe; // No register`
`endif	`endif

`//`	`//`
`// GPIO Interrupt Enable Register (or no register)`	`// GPIO Interrupt Enable Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_INTE	`ifdef GPIO_RGPIO_INTE
`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`	`reg [gw-1:0] rgpio_inte; // RGPIO_INTE register`
`else	`else
`wire [gw-1:0] rgpio_inte; // No register`	`wire [gw-1:0] rgpio_inte; // No register`
`endif	`endif

`//`	`//`
`// GPIO Positive edge Triggered Register (or no register)`	`// GPIO Positive edge Triggered Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_PTRIG	`ifdef GPIO_RGPIO_PTRIG
`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`	`reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register`
`else	`else
`wire [gw-1:0] rgpio_ptrig; // No register`	`wire [gw-1:0] rgpio_ptrig; // No register`
`endif	`endif

`//`	`//`
`// GPIO Auxiliary select Register (or no register)`	`// GPIO Auxiliary select Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_AUX	`ifdef GPIO_RGPIO_AUX
`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`	`reg [gw-1:0] rgpio_aux; // RGPIO_AUX register`
`else	`else
`wire [gw-1:0] rgpio_aux; // No register`	`wire [gw-1:0] rgpio_aux; // No register`
`endif	`endif

`//`	`//`
`// GPIO Control Register (or no register)`	`// GPIO Control Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_CTRL	`ifdef GPIO_RGPIO_CTRL
`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`	`reg [3:0] rgpio_ctrl; // RGPIO_CTRL register`
`else	`else
`wire [3:0] rgpio_ctrl; // No register`	`wire [3:0] rgpio_ctrl; // No register`
`endif	`endif

`//`	`//`
`// GPIO Interrupt Status Register (or no register)`	`// GPIO Interrupt Status Register (or no register)`
`//`	`//`
`ifdef GPIO_RGPIO_INTS	`ifdef GPIO_RGPIO_INTS
`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`	`reg [gw-1:0] rgpio_ints; // RGPIO_INTS register`
`else	`else
`wire [gw-1:0] rgpio_ints; // No register`	`wire [gw-1:0] rgpio_ints; // No register`
`endif	`endif

`//`	`//`
`// Internal wires & regs`	`// Internal wires & regs`
`//`	`//`
`wire rgpio_out_sel; // RGPIO_OUT select`	`wire rgpio_out_sel; // RGPIO_OUT select`
`wire rgpio_oe_sel; // RGPIO_OE select`	`wire rgpio_oe_sel; // RGPIO_OE select`
`wire rgpio_inte_sel; // RGPIO_INTE select`	`wire rgpio_inte_sel; // RGPIO_INTE select`
`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`	`wire rgpio_ptrig_sel;// RGPIO_PTRIG select`
`wire rgpio_aux_sel; // RGPIO_AUX select`	`wire rgpio_aux_sel; // RGPIO_AUX select`
`wire rgpio_ctrl_sel; // RGPIO_CTRL select`	`wire rgpio_ctrl_sel; // RGPIO_CTRL select`
`wire rgpio_ints_sel; // RGPIO_INTS select`	`wire rgpio_ints_sel; // RGPIO_INTS select`
`wire latch_clk; // Latch clock`	`wire latch_clk; // Latch clock`
`wire full_decoding; // Full address decoding qualification`	`wire full_decoding; // Full address decoding qualification`
`wire [gw-1:0] in_muxed; // Muxed inputs`	`wire [gw-1:0] in_muxed; // Muxed inputs`
`wire wb_ack; // WB Acknowledge`	`wire wb_ack; // WB Acknowledge`
`wire wb_err; // WB Error`	`wire wb_err; // WB Error`
`wire wb_inta; // WB Interrupt`	`wire wb_inta; // WB Interrupt`
`reg [dw-1:0] wb_dat; // WB Data out`	`reg [dw-1:0] wb_dat; // WB Data out`
`ifdef GPIO_REGISTERED_WB_OUTPUTS	`ifdef GPIO_REGISTERED_WB_OUTPUTS
`reg wb_ack_o; // WB Acknowledge`	`reg wb_ack_o; // WB Acknowledge`
`reg wb_err_o; // WB Error`	`reg wb_err_o; // WB Error`
`reg wb_inta_o; // WB Interrupt`	`reg wb_inta_o; // WB Interrupt`
`reg [dw-1:0] wb_dat_o; // WB Data out`	`reg [dw-1:0] wb_dat_o; // WB Data out`
`endif	`endif
`wire [gw-1:0] out_pad; // GPIO Outputs`	`wire [gw-1:0] out_pad; // GPIO Outputs`
`ifdef GPIO_REGISTERED_IO_OUTPUTS	`ifdef GPIO_REGISTERED_IO_OUTPUTS
`reg [gw-1:0] ext_pad_o; // GPIO Outputs`	`reg [gw-1:0] ext_pad_o; // GPIO Outputs`
`endif	`endif
`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`	`wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock`
`wire pext_clk; // External clock for posedge flops`	`wire pext_clk; // External clock for posedge flops`
`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`	`reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs`
`ifdef GPIO_NO_NEGEDGE_FLOPS	`ifdef GPIO_NO_NEGEDGE_FLOPS
`else	`else
`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`	`reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs`
`endif	`endif

`//`	`//`
`// All WISHBONE transfer terminations are successful except when:`	`// All WISHBONE transfer terminations are successful except when:`
`// a) full address decoding is enabled and address doesn't match`	`// a) full address decoding is enabled and address doesn't match`
`// any of the GPIO registers`	`// any of the GPIO registers`
`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`	`// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero`
`//`	`//`

`//`	`//`
`// WB Acknowledge`	`// WB Acknowledge`
`//`	`//`
`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`	`assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;`

`//`	`//`
`// Optional registration of WB Ack`	`// Optional registration of WB Ack`
`//`	`//`
`ifdef GPIO_REGISTERED_WB_OUTPUTS	`ifdef GPIO_REGISTERED_WB_OUTPUTS
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`wb_ack_o <= #1 1'b0;`	`wb_ack_o <= #1 1'b0;`
`else`	`else`
`wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;`	`wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;`
`else	`else
`assign wb_ack_o = wb_ack;`	`assign wb_ack_o = wb_ack;`
`endif	`endif

`//`	`//`
`// WB Error`	`// WB Error`
`//`	`//`
`ifdef GPIO_FULL_DECODE	`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS	`ifdef GPIO_STRICT_32BIT_ACCESS
`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`	`assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding \| (wb_sel_i != 4'b1111));`
`else	`else
`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`	`assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;`
`endif	`endif
`else	`else
`ifdef GPIO_STRICT_32BIT_ACCESS	`ifdef GPIO_STRICT_32BIT_ACCESS
`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`	`assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);`
`else	`else
`assign wb_err = 1'b0;`	`assign wb_err = 1'b0;`
`endif	`endif
`endif	`endif

`//`	`//`
`// Optional registration of WB error`	`// Optional registration of WB error`
`//`	`//`
`ifdef GPIO_REGISTERED_WB_OUTPUTS	`ifdef GPIO_REGISTERED_WB_OUTPUTS
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`wb_err_o <= #1 1'b0;`	`wb_err_o <= #1 1'b0;`
`else`	`else`
`wb_err_o <= #1 wb_err & ~wb_err_o;`	`wb_err_o <= #1 wb_err & ~wb_err_o;`
`else	`else
`assign wb_err_o = wb_err;`	`assign wb_err_o = wb_err;`
`endif	`endif

`//`	`//`
`// Full address decoder`	`// Full address decoder`
`//`	`//`
`ifdef GPIO_FULL_DECODE	`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &	assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});	(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else	`else
`assign full_decoding = 1'b1;`	`assign full_decoding = 1'b1;`
`endif	`endif

`//`	`//`
`// GPIO registers address decoder`	`// GPIO registers address decoder`
`//`	`//`
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;	assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;	assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;	assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;	assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;	assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;	assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;	assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;

`//`	`//`
`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`	`// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit`
`//`	`//`
`ifdef GPIO_RGPIO_CTRL	`ifdef GPIO_RGPIO_CTRL
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`rgpio_ctrl <= #1 4'b0;`	`rgpio_ctrl <= #1 4'b0;`
`else if (rgpio_ctrl_sel && wb_we_i)`	`else if (rgpio_ctrl_sel && wb_we_i)`
`rgpio_ctrl <= #1 wb_dat_i[3:0];`	`rgpio_ctrl <= #1 wb_dat_i[3:0];`
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])	else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;	rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] \| wb_inta_o;
`else	`else
`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`	`assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1`
`endif	`endif

`//`	`//`
`// Write to RGPIO_OUT`	`// Write to RGPIO_OUT`
`//`	`//`
`ifdef GPIO_RGPIO_OUT	`ifdef GPIO_RGPIO_OUT
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`rgpio_out <= #1 {gw{1'b0}};`	`rgpio_out <= #1 {gw{1'b0}};`
`else if (rgpio_out_sel && wb_we_i)`	`else if (rgpio_out_sel && wb_we_i)`
`begin`	`begin`
`ifdef GPIO_STRICT_32BIT_ACCESS	`ifdef GPIO_STRICT_32BIT_ACCESS
`rgpio_out <= #1 wb_dat_i[gw-1:0];`	`rgpio_out <= #1 wb_dat_i[gw-1:0];`
`endif	`endif

`ifdef GPIO_WB_BYTES4	`ifdef GPIO_WB_BYTES4
`if ( wb_sel_i [3] == 1'b1 )`	`if ( wb_sel_i [3] == 1'b1 )`
`rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;`	`rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;`
`if ( wb_sel_i [2] == 1'b1 )`	`if ( wb_sel_i [2] == 1'b1 )`
`rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;`	`rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;`
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;`	`rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;`	`rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES3	`ifdef GPIO_WB_BYTES3
`if ( wb_sel_i [2] == 1'b1 )`	`if ( wb_sel_i [2] == 1'b1 )`
`rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;`	`rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;`
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;`	`rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;`	`rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES2	`ifdef GPIO_WB_BYTES2
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;`	`rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;`	`rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES1	`ifdef GPIO_WB_BYTES1
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;`	`rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;`
`endif	`endif
`end`	`end`

`else	`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0	assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif	`endif

`//`	`//`
`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`	`// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.`
`//`	`//`
`ifdef GPIO_RGPIO_OE	`ifdef GPIO_RGPIO_OE
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`rgpio_oe <= #1 {gw{1'b0}};`	`rgpio_oe <= #1 {gw{1'b0}};`
`else if (rgpio_oe_sel && wb_we_i)`	`else if (rgpio_oe_sel && wb_we_i)`
`begin`	`begin`
`ifdef GPIO_STRICT_32BIT_ACCESS	`ifdef GPIO_STRICT_32BIT_ACCESS
`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`	`rgpio_oe <= #1 ~wb_dat_i[gw-1:0];`
`endif	`endif

`ifdef GPIO_WB_BYTES4	`ifdef GPIO_WB_BYTES4
`if ( wb_sel_i [3] == 1'b1 )`	`if ( wb_sel_i [3] == 1'b1 )`
`rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;`	`rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;`
`if ( wb_sel_i [2] == 1'b1 )`	`if ( wb_sel_i [2] == 1'b1 )`
`rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;`	`rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;`
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;`	`rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;`	`rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES3	`ifdef GPIO_WB_BYTES3
`if ( wb_sel_i [2] == 1'b1 )`	`if ( wb_sel_i [2] == 1'b1 )`
`rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;`	`rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;`
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;`	`rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;`	`rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES2	`ifdef GPIO_WB_BYTES2
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;`	`rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;`	`rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES1	`ifdef GPIO_WB_BYTES1
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;`	`rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;`
`endif	`endif
`end`	`end`

`else	`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0	assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
`endif	`endif

`//`	`//`
`// Write to RGPIO_INTE`	`// Write to RGPIO_INTE`
`//`	`//`
`ifdef GPIO_RGPIO_INTE	`ifdef GPIO_RGPIO_INTE
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`rgpio_inte <= #1 {gw{1'b0}};`	`rgpio_inte <= #1 {gw{1'b0}};`
`else if (rgpio_inte_sel && wb_we_i)`	`else if (rgpio_inte_sel && wb_we_i)`
`begin`	`begin`
`ifdef GPIO_STRICT_32BIT_ACCESS	`ifdef GPIO_STRICT_32BIT_ACCESS
`rgpio_inte <= #1 wb_dat_i[gw-1:0];`	`rgpio_inte <= #1 wb_dat_i[gw-1:0];`
`endif	`endif

`ifdef GPIO_WB_BYTES4	`ifdef GPIO_WB_BYTES4
`if ( wb_sel_i [3] == 1'b1 )`	`if ( wb_sel_i [3] == 1'b1 )`
`rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;`	`rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;`
`if ( wb_sel_i [2] == 1'b1 )`	`if ( wb_sel_i [2] == 1'b1 )`
`rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;`	`rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;`
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;`	`rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;`	`rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES3	`ifdef GPIO_WB_BYTES3
`if ( wb_sel_i [2] == 1'b1 )`	`if ( wb_sel_i [2] == 1'b1 )`
`rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;`	`rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;`
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;`	`rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;`	`rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES2	`ifdef GPIO_WB_BYTES2
`if ( wb_sel_i [1] == 1'b1 )`	`if ( wb_sel_i [1] == 1'b1 )`
`rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;`	`rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;`
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;`	`rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;`
`endif	`endif
`ifdef GPIO_WB_BYTES1	`ifdef GPIO_WB_BYTES1
`if ( wb_sel_i [0] == 1'b1 )`	`if ( wb_sel_i [0] == 1'b1 )`
`rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;`	`rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;`
`endif	`endif
`end`	`end`


`else	`else
assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0	assign rgpio_inte = `GPIO_DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
`endif	`endif

`//`	`//`
`// Write to RGPIO_PTRIG`	`// Write to RGPIO_PTRIG`
`//`	`//`
`ifdef GPIO_RGPIO_PTRIG	`ifdef GPIO_RGPIO_PTRIG
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`rgpio_ptrig <= #1 {gw{1'b0}};`	`rgpio_ptrig <= #1 {gw{1'b0}};`
`else if (rgpio_ptrig_sel && wb_we_i)`	`else if (rgpio_ptrig_sel && wb_we_i)`
`begin`	`begin`
`ifdef GPIO_STRICT_32BIT_ACCESS	`ifdef GPIO_STRICT_32BIT_ACCESS
`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`	`rgpio_ptrig <= #1 wb_dat_i[gw-1:0];`

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  WISHBONE General-Purpose I/O                                ////

////  WISHBONE General-Purpose I/O                                ////

////                                                              ////

////                                                              ////

////  This file is part of the GPIO project                       ////

////  This file is part of the GPIO project                       ////

////  http://www.opencores.org/cores/gpio/                        ////

////  http://www.opencores.org/cores/gpio/                        ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Implementation of GPIO IP core according to                 ////

////  Implementation of GPIO IP core according to                 ////

////  GPIO IP core specification document.                        ////

////  GPIO IP core specification document.                        ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   Nothing                                                    ////

////   Nothing                                                    ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.14  2003/11/06 13:59:07  gorand

// Revision 1.14  2003/11/06 13:59:07  gorand

// added support for 8-bit access to registers.

// added support for 8-bit access to registers.

//

//

// Revision 1.13  2002/11/18 22:35:18  lampret

// Revision 1.13  2002/11/18 22:35:18  lampret

// Bug fix. Interrupts were also asserted when condition was not met.

// Bug fix. Interrupts were also asserted when condition was not met.

//

//

// Revision 1.12  2002/11/11 21:36:28  lampret

// Revision 1.12  2002/11/11 21:36:28  lampret

// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].

// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].

//

//

// Revision 1.11  2002/03/13 20:56:28  lampret

// Revision 1.11  2002/03/13 20:56:28  lampret

// Removed zero padding as per Avi Shamli suggestion.

// Removed zero padding as per Avi Shamli suggestion.

//

//

// Revision 1.10  2002/03/13 20:47:57  lampret

// Revision 1.10  2002/03/13 20:47:57  lampret

// Ports changed per Ran Aviram suggestions.

// Ports changed per Ran Aviram suggestions.

//

//

// Revision 1.9  2002/03/09 03:43:27  lampret

// Revision 1.9  2002/03/09 03:43:27  lampret

// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)

// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)

//

//

// Revision 1.8  2002/01/14 19:06:28  lampret

// Revision 1.8  2002/01/14 19:06:28  lampret

// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.

// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.

//

//

// Revision 1.7  2001/12/25 17:21:21  lampret

// Revision 1.7  2001/12/25 17:21:21  lampret

// Fixed two typos.

// Fixed two typos.

//

//

// Revision 1.6  2001/12/25 17:12:35  lampret

// Revision 1.6  2001/12/25 17:12:35  lampret

// Added RGPIO_INTS.

// Added RGPIO_INTS.

//

//

// Revision 1.5  2001/12/12 20:35:53  lampret

// Revision 1.5  2001/12/12 20:35:53  lampret

// Fixing style.

// Fixing style.

//

//

// Revision 1.4  2001/12/12 07:12:58  lampret

// Revision 1.4  2001/12/12 07:12:58  lampret

// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)

// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)

//

//

// Revision 1.3  2001/11/15 02:24:37  lampret

// Revision 1.3  2001/11/15 02:24:37  lampret

// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.

// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.

//

//

// Revision 1.2  2001/10/31 02:26:51  lampret

// Revision 1.2  2001/10/31 02:26:51  lampret

// Fixed wb_err_o.

// Fixed wb_err_o.

//

//

// Revision 1.1  2001/09/18 18:49:07  lampret

// Revision 1.1  2001/09/18 18:49:07  lampret

// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.

// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.

//

//

// Revision 1.1  2001/08/21 21:39:28  lampret

// Revision 1.1  2001/08/21 21:39:28  lampret

// Changed directory structure, port names and drfines.

// Changed directory structure, port names and drfines.

//

//

// Revision 1.2  2001/07/14 20:39:26  lampret

// Revision 1.2  2001/07/14 20:39:26  lampret

// Better configurability.

// Better configurability.

//

//

// Revision 1.1  2001/06/05 07:45:26  lampret

// Revision 1.1  2001/06/05 07:45:26  lampret

// Added initial RTL and test benches. There are still some issues with these files.

// Added initial RTL and test benches. There are still some issues with these files.

//

//

//

//

// synopsys translate_off

// synopsys translate_off

`include "timescale.v"

`include "timescale.v"

// synopsys translate_on

// synopsys translate_on

`include "gpio_defines.v"

`include "gpio_defines.v"

module gpio_top(

module gpio_top(

        // WISHBONE Interface

        // WISHBONE Interface

        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,

        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,

        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,

        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,

        // Auxiliary inputs interface

        // Auxiliary inputs interface

        aux_i,

        aux_i,

        // External GPIO Interface

        // External GPIO Interface

        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o

        ext_pad_i, clk_pad_i, ext_pad_o, ext_padoen_o

);

);

parameter dw = 32;

parameter dw = 32;

parameter aw = `GPIO_ADDRHH+1;

parameter aw = `GPIO_ADDRHH+1;

parameter gw = `GPIO_IOS;

parameter gw = `GPIO_IOS;

//

//

// WISHBONE Interface

// WISHBONE Interface

//

//

input                   wb_clk_i;       // Clock

input                   wb_clk_i;       // Clock

input                   wb_rst_i;       // Reset

input                   wb_rst_i;       // Reset

input                   wb_cyc_i;       // cycle valid input

input                   wb_cyc_i;       // cycle valid input

input   [aw-1:0] wb_adr_i;       // address bus inputs

input   [aw-1:0] wb_adr_i;       // address bus inputs

input   [dw-1:0] wb_dat_i;       // input data bus

input   [dw-1:0] wb_dat_i;       // input data bus

input   [3:0]            wb_sel_i;       // byte select inputs

input   [3:0]            wb_sel_i;       // byte select inputs

input                   wb_we_i;        // indicates write transfer

input                   wb_we_i;        // indicates write transfer

input                   wb_stb_i;       // strobe input

input                   wb_stb_i;       // strobe input

output  [dw-1:0] wb_dat_o;       // output data bus

output  [dw-1:0] wb_dat_o;       // output data bus

output                  wb_ack_o;       // normal termination

output                  wb_ack_o;       // normal termination

output                  wb_err_o;       // termination w/ error

output                  wb_err_o;       // termination w/ error

output                  wb_inta_o;      // Interrupt request output

output                  wb_inta_o;      // Interrupt request output

// Auxiliary Inputs Interface

// Auxiliary Inputs Interface

input   [gw-1:0] aux_i;          // Auxiliary inputs

input   [gw-1:0] aux_i;          // Auxiliary inputs

//

//

// External GPIO Interface

// External GPIO Interface

//

//

input   [gw-1:0] ext_pad_i;      // GPIO Inputs

input   [gw-1:0] ext_pad_i;      // GPIO Inputs

input                   clk_pad_i;      // GPIO Eclk

input                   clk_pad_i;      // GPIO Eclk

output  [gw-1:0] ext_pad_o;      // GPIO Outputs

output  [gw-1:0] ext_pad_o;      // GPIO Outputs

output  [gw-1:0] ext_padoen_o;   // GPIO output drivers enables

output  [gw-1:0] ext_padoen_o;   // GPIO output drivers enables

`ifdef GPIO_IMPLEMENTED

`ifdef GPIO_IMPLEMENTED

//

//

// GPIO Input Register (or no register)

// GPIO Input Register (or no register)

//

//

`ifdef GPIO_RGPIO_IN

`ifdef GPIO_RGPIO_IN

reg     [gw-1:0] rgpio_in;       // RGPIO_IN register

reg     [gw-1:0] rgpio_in;       // RGPIO_IN register

`else

`else

wire    [gw-1:0] rgpio_in;       // No register

wire    [gw-1:0] rgpio_in;       // No register

`endif

`endif

//

//

// GPIO Output Register (or no register)

// GPIO Output Register (or no register)

//

//

`ifdef GPIO_RGPIO_OUT

`ifdef GPIO_RGPIO_OUT

reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register

reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register

`else

`else

wire    [gw-1:0] rgpio_out;      // No register

wire    [gw-1:0] rgpio_out;      // No register

`endif

`endif

//

//

// GPIO Output Driver Enable Register (or no register)

// GPIO Output Driver Enable Register (or no register)

//

//

`ifdef GPIO_RGPIO_OE

`ifdef GPIO_RGPIO_OE

reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register

reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register

`else

`else

wire    [gw-1:0] rgpio_oe;       // No register

wire    [gw-1:0] rgpio_oe;       // No register

`endif

`endif

//

//

// GPIO Interrupt Enable Register (or no register)

// GPIO Interrupt Enable Register (or no register)

//

//

`ifdef GPIO_RGPIO_INTE

`ifdef GPIO_RGPIO_INTE

reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register

reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register

`else

`else

wire    [gw-1:0] rgpio_inte;     // No register

wire    [gw-1:0] rgpio_inte;     // No register

`endif

`endif

//

//

// GPIO Positive edge Triggered Register (or no register)

// GPIO Positive edge Triggered Register (or no register)

//

//

`ifdef GPIO_RGPIO_PTRIG

`ifdef GPIO_RGPIO_PTRIG

reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register

reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register

`else

`else

wire    [gw-1:0] rgpio_ptrig;    // No register

wire    [gw-1:0] rgpio_ptrig;    // No register

`endif

`endif

//

//

// GPIO Auxiliary select Register (or no register)

// GPIO Auxiliary select Register (or no register)

//

//

`ifdef GPIO_RGPIO_AUX

`ifdef GPIO_RGPIO_AUX

reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register

reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register

`else

`else

wire    [gw-1:0] rgpio_aux;      // No register

wire    [gw-1:0] rgpio_aux;      // No register

`endif

`endif

//

//

// GPIO Control Register (or no register)

// GPIO Control Register (or no register)

//

//

`ifdef GPIO_RGPIO_CTRL

`ifdef GPIO_RGPIO_CTRL

reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register

reg     [3:0]            rgpio_ctrl;     // RGPIO_CTRL register

`else

`else

wire    [3:0]            rgpio_ctrl;     // No register

wire    [3:0]            rgpio_ctrl;     // No register

`endif

`endif

//

//

// GPIO Interrupt Status Register (or no register)

// GPIO Interrupt Status Register (or no register)

//

//

`ifdef GPIO_RGPIO_INTS

`ifdef GPIO_RGPIO_INTS

reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register

reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register

`else

`else

wire    [gw-1:0] rgpio_ints;     // No register

wire    [gw-1:0] rgpio_ints;     // No register

`endif

`endif

//

//

// Internal wires & regs

// Internal wires & regs

//

//

wire                    rgpio_out_sel;  // RGPIO_OUT select

wire                    rgpio_out_sel;  // RGPIO_OUT select

wire                    rgpio_oe_sel;   // RGPIO_OE select

wire                    rgpio_oe_sel;   // RGPIO_OE select

wire                    rgpio_inte_sel; // RGPIO_INTE select

wire                    rgpio_inte_sel; // RGPIO_INTE select

wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select

wire                    rgpio_ptrig_sel;// RGPIO_PTRIG select

wire                    rgpio_aux_sel;  // RGPIO_AUX select

wire                    rgpio_aux_sel;  // RGPIO_AUX select

wire                    rgpio_ctrl_sel; // RGPIO_CTRL select

wire                    rgpio_ctrl_sel; // RGPIO_CTRL select

wire                    rgpio_ints_sel; // RGPIO_INTS select

wire                    rgpio_ints_sel; // RGPIO_INTS select

wire                    latch_clk;      // Latch clock

wire                    latch_clk;      // Latch clock

wire                    full_decoding;  // Full address decoding qualification

wire                    full_decoding;  // Full address decoding qualification

wire    [gw-1:0] in_muxed;       // Muxed inputs

wire    [gw-1:0] in_muxed;       // Muxed inputs

wire                    wb_ack;         // WB Acknowledge

wire                    wb_ack;         // WB Acknowledge

wire                    wb_err;         // WB Error

wire                    wb_err;         // WB Error

wire                    wb_inta;        // WB Interrupt

wire                    wb_inta;        // WB Interrupt

reg     [dw-1:0] wb_dat;         // WB Data out

reg     [dw-1:0] wb_dat;         // WB Data out

`ifdef GPIO_REGISTERED_WB_OUTPUTS

`ifdef GPIO_REGISTERED_WB_OUTPUTS

reg                     wb_ack_o;       // WB Acknowledge

reg                     wb_ack_o;       // WB Acknowledge

reg                     wb_err_o;       // WB Error

reg                     wb_err_o;       // WB Error

reg                     wb_inta_o;      // WB Interrupt

reg                     wb_inta_o;      // WB Interrupt

reg     [dw-1:0] wb_dat_o;       // WB Data out

reg     [dw-1:0] wb_dat_o;       // WB Data out

`endif

`endif

wire    [gw-1:0] out_pad;        // GPIO Outputs

wire    [gw-1:0] out_pad;        // GPIO Outputs

`ifdef GPIO_REGISTERED_IO_OUTPUTS

`ifdef GPIO_REGISTERED_IO_OUTPUTS

reg     [gw-1:0] ext_pad_o;      // GPIO Outputs

reg     [gw-1:0] ext_pad_o;      // GPIO Outputs

`endif

`endif

wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock

wire    [gw-1:0] extc_in;        // Muxed inputs sampled by external clock

wire                    pext_clk;       // External clock for posedge flops

wire                    pext_clk;       // External clock for posedge flops

reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs

reg     [gw-1:0] pextc_sampled;  // Posedge external clock sampled inputs

`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_NEGEDGE_FLOPS

`else

`else

reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs

reg     [gw-1:0] nextc_sampled;  // Negedge external clock sampled inputs

`endif

`endif

//

//

// All WISHBONE transfer terminations are successful except when:

// All WISHBONE transfer terminations are successful except when:

// a) full address decoding is enabled and address doesn't match

// a) full address decoding is enabled and address doesn't match

//    any of the GPIO registers

//    any of the GPIO registers

// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero

// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero

//

//

//

//

// WB Acknowledge

// WB Acknowledge

//

//

assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;

assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;

//

//

// Optional registration of WB Ack

// Optional registration of WB Ack

//

//

`ifdef GPIO_REGISTERED_WB_OUTPUTS

`ifdef GPIO_REGISTERED_WB_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                wb_ack_o <= #1 1'b0;

                wb_ack_o <= #1 1'b0;

        else

        else

                wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;

                wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;

`else

`else

assign wb_ack_o = wb_ack;

assign wb_ack_o = wb_ack;

`endif

`endif

//

//

// WB Error

// WB Error

//

//

`ifdef GPIO_FULL_DECODE

`ifdef GPIO_FULL_DECODE

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));

assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));

`else

`else

assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;

assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;

`endif

`endif

`else

`else

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);

assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);

`else

`else

assign wb_err = 1'b0;

assign wb_err = 1'b0;

`endif

`endif

`endif

`endif

//

//

// Optional registration of WB error

// Optional registration of WB error

//

//

`ifdef GPIO_REGISTERED_WB_OUTPUTS

`ifdef GPIO_REGISTERED_WB_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                wb_err_o <= #1 1'b0;

                wb_err_o <= #1 1'b0;

        else

        else

                wb_err_o <= #1 wb_err & ~wb_err_o;

                wb_err_o <= #1 wb_err & ~wb_err_o;

`else

`else

assign wb_err_o = wb_err;

assign wb_err_o = wb_err;

`endif

`endif

//

//

// Full address decoder

// Full address decoder

//

//

`ifdef GPIO_FULL_DECODE

`ifdef GPIO_FULL_DECODE

assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &

assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &

                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});

                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});

`else

`else

assign full_decoding = 1'b1;

assign full_decoding = 1'b1;

`endif

`endif

//

//

// GPIO registers address decoder

// GPIO registers address decoder

//

//

assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;

assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;

assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;

assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;

assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;

assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;

assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;

assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;

assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;

assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;

assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;

assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;

assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;

assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;

//

//

// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit

// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit

//

//

`ifdef GPIO_RGPIO_CTRL

`ifdef GPIO_RGPIO_CTRL

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_ctrl <= #1 4'b0;

                rgpio_ctrl <= #1 4'b0;

        else if (rgpio_ctrl_sel && wb_we_i)

        else if (rgpio_ctrl_sel && wb_we_i)

                rgpio_ctrl <= #1 wb_dat_i[3:0];

                rgpio_ctrl <= #1 wb_dat_i[3:0];

        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])

        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])

                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;

                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;

`else

`else

assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1

assign rgpio_ctrl = 4'h01;      // RGPIO_CTRL[EN] = 1

`endif

`endif

//

//

// Write to RGPIO_OUT

// Write to RGPIO_OUT

//

//

`ifdef GPIO_RGPIO_OUT

`ifdef GPIO_RGPIO_OUT

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_out <= #1 {gw{1'b0}};

                rgpio_out <= #1 {gw{1'b0}};

        else if (rgpio_out_sel && wb_we_i)

        else if (rgpio_out_sel && wb_we_i)

    begin

    begin

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

                rgpio_out <= #1 wb_dat_i[gw-1:0];

                rgpio_out <= #1 wb_dat_i[gw-1:0];

`endif

`endif

`ifdef GPIO_WB_BYTES4

`ifdef GPIO_WB_BYTES4

     if ( wb_sel_i [3] == 1'b1 )

     if ( wb_sel_i [3] == 1'b1 )

       rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

       rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;

       rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES3

`ifdef GPIO_WB_BYTES3

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

       rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES2

`ifdef GPIO_WB_BYTES2

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

       rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES1

`ifdef GPIO_WB_BYTES1

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

       rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

`endif

`endif

end

end

`else

`else

assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0

assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0

`endif

`endif

//

//

// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.

// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.

//

//

`ifdef GPIO_RGPIO_OE

`ifdef GPIO_RGPIO_OE

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_oe <= #1 {gw{1'b0}};

                rgpio_oe <= #1 {gw{1'b0}};

        else if (rgpio_oe_sel && wb_we_i)

        else if (rgpio_oe_sel && wb_we_i)

  begin

  begin

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];

                rgpio_oe <= #1 ~wb_dat_i[gw-1:0];

`endif

`endif

`ifdef GPIO_WB_BYTES4

`ifdef GPIO_WB_BYTES4

     if ( wb_sel_i [3] == 1'b1 )

     if ( wb_sel_i [3] == 1'b1 )

       rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;

       rgpio_oe [gw-1:24] <= #1 ~wb_dat_i [gw-1:24] ;

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;

       rgpio_oe [23:16] <= #1 ~wb_dat_i [23:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;

       rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;

       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES3

`ifdef GPIO_WB_BYTES3

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;

       rgpio_oe [gw-1:16] <= #1 ~wb_dat_i [gw-1:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;

       rgpio_oe [15:8] <= #1 ~wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;

       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES2

`ifdef GPIO_WB_BYTES2

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;

       rgpio_oe [gw-1:8] <= #1 ~wb_dat_i [gw-1:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;

       rgpio_oe [7:0] <= #1 ~wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES1

`ifdef GPIO_WB_BYTES1

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;

       rgpio_oe [gw-1:0] <= #1 ~wb_dat_i [gw-1:0] ;

`endif

`endif

end

end

`else

`else

assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0

assign rgpio_oe = `GPIO_DEF_RPGIO_OE;   // RGPIO_OE = 0x0

`endif

`endif

//

//

// Write to RGPIO_INTE

// Write to RGPIO_INTE

//

//

`ifdef GPIO_RGPIO_INTE

`ifdef GPIO_RGPIO_INTE

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_inte <= #1 {gw{1'b0}};

                rgpio_inte <= #1 {gw{1'b0}};

        else if (rgpio_inte_sel && wb_we_i)

        else if (rgpio_inte_sel && wb_we_i)

  begin

  begin

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

                rgpio_inte <= #1 wb_dat_i[gw-1:0];

                rgpio_inte <= #1 wb_dat_i[gw-1:0];

`endif

`endif

`ifdef GPIO_WB_BYTES4

`ifdef GPIO_WB_BYTES4

     if ( wb_sel_i [3] == 1'b1 )

     if ( wb_sel_i [3] == 1'b1 )

       rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

       rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;

       rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES3

`ifdef GPIO_WB_BYTES3

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

       rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES2

`ifdef GPIO_WB_BYTES2

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

       rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES1

`ifdef GPIO_WB_BYTES1

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

       rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

`endif

`endif

end

end

`else

`else

assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0

assign rgpio_inte = `GPIO_DEF_RPGIO_INTE;       // RGPIO_INTE = 0x0

`endif

`endif

//

//

// Write to RGPIO_PTRIG

// Write to RGPIO_PTRIG

//

//

`ifdef GPIO_RGPIO_PTRIG

`ifdef GPIO_RGPIO_PTRIG

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_ptrig <= #1 {gw{1'b0}};

                rgpio_ptrig <= #1 {gw{1'b0}};

        else if (rgpio_ptrig_sel && wb_we_i)

        else if (rgpio_ptrig_sel && wb_we_i)

  begin

  begin

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];

                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];

`endif

`endif

`ifdef GPIO_WB_BYTES4

`ifdef GPIO_WB_BYTES4

     if ( wb_sel_i [3] == 1'b1 )

     if ( wb_sel_i [3] == 1'b1 )

       rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

       rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;

       rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES3

`ifdef GPIO_WB_BYTES3

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

       rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES2

`ifdef GPIO_WB_BYTES2

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

       rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES1

`ifdef GPIO_WB_BYTES1

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

       rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

`endif

`endif

end

end

`else

`else

assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0

assign rgpio_ptrig = `GPIO_DEF_RPGIO_PTRIG;     // RGPIO_PTRIG = 0x0

`endif

`endif

//

//

// Write to RGPIO_AUX

// Write to RGPIO_AUX

//

//

`ifdef GPIO_RGPIO_AUX

`ifdef GPIO_RGPIO_AUX

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_aux <= #1 {gw{1'b0}};

                rgpio_aux <= #1 {gw{1'b0}};

        else if (rgpio_aux_sel && wb_we_i)

        else if (rgpio_aux_sel && wb_we_i)

  begin

  begin

`ifdef GPIO_STRICT_32BIT_ACCESS

`ifdef GPIO_STRICT_32BIT_ACCESS

                rgpio_aux <= #1 wb_dat_i[gw-1:0];

                rgpio_aux <= #1 wb_dat_i[gw-1:0];

`endif

`endif

`ifdef GPIO_WB_BYTES4

`ifdef GPIO_WB_BYTES4

     if ( wb_sel_i [3] == 1'b1 )

     if ( wb_sel_i [3] == 1'b1 )

       rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

       rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;

       rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES3

`ifdef GPIO_WB_BYTES3

     if ( wb_sel_i [2] == 1'b1 )

     if ( wb_sel_i [2] == 1'b1 )

       rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

       rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;

       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES2

`ifdef GPIO_WB_BYTES2

     if ( wb_sel_i [1] == 1'b1 )

     if ( wb_sel_i [1] == 1'b1 )

       rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

       rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;

       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;

`endif

`endif

`ifdef GPIO_WB_BYTES1

`ifdef GPIO_WB_BYTES1

     if ( wb_sel_i [0] == 1'b1 )

     if ( wb_sel_i [0] == 1'b1 )

       rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

       rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;

`endif

`endif

end

end

`else

`else

assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0

assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0

`endif

`endif

//

//

// Latch into RGPIO_IN

// Latch into RGPIO_IN

//

//

`ifdef GPIO_RGPIO_IN

`ifdef GPIO_RGPIO_IN

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_in <= #1 {gw{1'b0}};

                rgpio_in <= #1 {gw{1'b0}};

        else

        else

                rgpio_in <= #1 in_muxed;

                rgpio_in <= #1 in_muxed;

`else

`else

assign rgpio_in = in_muxed;

assign rgpio_in = in_muxed;

`endif

`endif

//

//

// Mux inputs directly from input pads with inputs sampled by external clock

// Mux inputs directly from input pads with inputs sampled by external clock

//

//

assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;

assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i;

//

//

// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.

// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.

// If negedge flops are allowed, pext_clk only clocks posedge flops.

// If negedge flops are allowed, pext_clk only clocks posedge flops.

//

//

`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_CLKPAD_LOGIC

`ifdef GPIO_NO_CLKPAD_LOGIC

assign pext_clk = clk_pad_i;

assign pext_clk = clk_pad_i;

`else

`else

assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;

assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i;

`endif

`endif

`else

`else

assign pext_clk = clk_pad_i;

assign pext_clk = clk_pad_i;

`endif

`endif

//

//

// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.

// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.

//

//

`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_NEGEDGE_FLOPS

assign extc_in = pextc_sampled;

assign extc_in = pextc_sampled;

`else

`else

assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;

assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;

`endif

`endif

//

//

// Latch using posedge external clock

// Latch using posedge external clock

//

//

always @(posedge pext_clk or posedge wb_rst_i)

always @(posedge pext_clk or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                pextc_sampled <= #1 {gw{1'b0}};

                pextc_sampled <= #1 {gw{1'b0}};

        else

        else

                pextc_sampled <= #1 ext_pad_i;

                pextc_sampled <= #1 ext_pad_i;

//

//

// Latch using negedge external clock

// Latch using negedge external clock

//

//

`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_NEGEDGE_FLOPS

`else

`else

always @(negedge clk_pad_i or posedge wb_rst_i)

always @(negedge clk_pad_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                nextc_sampled <= #1 {gw{1'b0}};

                nextc_sampled <= #1 {gw{1'b0}};

        else

        else

                nextc_sampled <= #1 ext_pad_i;

                nextc_sampled <= #1 ext_pad_i;

`endif

`endif

//

//

// Mux all registers when doing a read of GPIO registers

// Mux all registers when doing a read of GPIO registers

//

//

always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or

always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or

                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)

                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints)

        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case

        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case

`ifdef GPIO_READREGS

`ifdef GPIO_READREGS

                `GPIO_RGPIO_OUT: begin

                `GPIO_RGPIO_OUT: begin

                        wb_dat[dw-1:0] = rgpio_out;

                        wb_dat[dw-1:0] = rgpio_out;

end

end

                `GPIO_RGPIO_OE: begin

                `GPIO_RGPIO_OE: begin

                        wb_dat[dw-1:0] = ~rgpio_oe;

                        wb_dat[dw-1:0] = ~rgpio_oe;

end

end

                `GPIO_RGPIO_INTE: begin

                `GPIO_RGPIO_INTE: begin

                        wb_dat[dw-1:0] = rgpio_inte;

                        wb_dat[dw-1:0] = rgpio_inte;

end

end

                `GPIO_RGPIO_PTRIG: begin

                `GPIO_RGPIO_PTRIG: begin

                        wb_dat[dw-1:0] = rgpio_ptrig;

                        wb_dat[dw-1:0] = rgpio_ptrig;

end

end

                `GPIO_RGPIO_AUX: begin

                `GPIO_RGPIO_AUX: begin

                        wb_dat[dw-1:0] = rgpio_aux;

                        wb_dat[dw-1:0] = rgpio_aux;

end

end

                `GPIO_RGPIO_CTRL: begin

                `GPIO_RGPIO_CTRL: begin

                        wb_dat[3:0] = rgpio_ctrl;

                        wb_dat[3:0] = rgpio_ctrl;

                        wb_dat[dw-1:4] = {dw-4{1'b0}};

                        wb_dat[dw-1:4] = {dw-4{1'b0}};

end

end

`endif

`endif

                `GPIO_RGPIO_INTS: begin

                `GPIO_RGPIO_INTS: begin

                        wb_dat[dw-1:0] = rgpio_ints;

                        wb_dat[dw-1:0] = rgpio_ints;

end

end

                default: begin

                default: begin

                        wb_dat[dw-1:0] = rgpio_in;

                        wb_dat[dw-1:0] = rgpio_in;

end

end

        endcase

        endcase

//

//

// WB data output

// WB data output

//

//

`ifdef GPIO_REGISTERED_WB_OUTPUTS

`ifdef GPIO_REGISTERED_WB_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                wb_dat_o <= #1 {dw{1'b0}};

                wb_dat_o <= #1 {dw{1'b0}};

        else

        else

                wb_dat_o <= #1 wb_dat;

                wb_dat_o <= #1 wb_dat;

`else

`else

assign wb_dat_o = wb_dat;

assign wb_dat_o = wb_dat;

`endif

`endif

//

//

// RGPIO_INTS

// RGPIO_INTS

//

//

`ifdef GPIO_RGPIO_INTS

`ifdef GPIO_RGPIO_INTS

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                rgpio_ints <= #1 {gw{1'b0}};

                rgpio_ints <= #1 {gw{1'b0}};

        else if (rgpio_ints_sel && wb_we_i)

        else if (rgpio_ints_sel && wb_we_i)

                rgpio_ints <= #1 wb_dat_i[gw-1:0];

                rgpio_ints <= #1 wb_dat_i[gw-1:0];

        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])

        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])

                rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);

                rgpio_ints <= #1 (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);

`else

`else

assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);

assign rgpio_ints = (rgpio_ints | ((ext_pad_i ^ rgpio_in) & ~(ext_pad_i ^ rgpio_ptrig)) & rgpio_inte);

`endif

`endif

//

//

// Generate interrupt request

// Generate interrupt request

//

//

assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;

assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;

//

//

// Optional registration of WB interrupt

// Optional registration of WB interrupt

//

//

`ifdef GPIO_REGISTERED_WB_OUTPUTS

`ifdef GPIO_REGISTERED_WB_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                wb_inta_o <= #1 1'b0;

                wb_inta_o <= #1 1'b0;

        else

        else

                wb_inta_o <= #1 wb_inta;

                wb_inta_o <= #1 wb_inta;

`else

`else

assign wb_inta_o = wb_inta;

assign wb_inta_o = wb_inta;

`endif

`endif

//

//

// Output enables are RGPIO_OE bits

// Output enables are RGPIO_OE bits

//

//

assign ext_padoen_o = rgpio_oe;

assign ext_padoen_o = rgpio_oe;

//

//

// Generate GPIO outputs

// Generate GPIO outputs

//

//

assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;

assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;

//

//

// Optional registration of GPIO outputs

// Optional registration of GPIO outputs

//

//

`ifdef GPIO_REGISTERED_IO_OUTPUTS

`ifdef GPIO_REGISTERED_IO_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

        if (wb_rst_i)

                ext_pad_o <= #1 {gw{1'b0}};

                ext_pad_o <= #1 {gw{1'b0}};

        else

        else

                ext_pad_o <= #1 out_pad;

                ext_pad_o <= #1 out_pad;

`else

`else

assign ext_pad_o = out_pad;

assign ext_pad_o = out_pad;

`endif

`endif

`else

`else

//

//

// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL

// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL

// is cleared and WISHBONE transfers complete with errors

// is cleared and WISHBONE transfers complete with errors

//

//

assign wb_inta_o = 1'b0;

assign wb_inta_o = 1'b0;

assign wb_ack_o = 1'b0;

assign wb_ack_o = 1'b0;

assign wb_err_o = wb_cyc_i & wb_stb_i;

assign wb_err_o = wb_cyc_i & wb_stb_i;

assign ext_padoen_o = {gw{1'b1}};

assign ext_padoen_o = {gw{1'b1}};

assign ext_pad_o = {gw{1'b0}};

assign ext_pad_o = {gw{1'b0}};

//

//

// Read GPIO registers

// Read GPIO registers

//

//

assign wb_dat_o = {dw{1'b0}};

assign wb_dat_o = {dw{1'b0}};

`endif

`endif

endmodule

endmodule

Browse

Tools

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] [gpio_top.v] - Diff between revs 46 and 65