//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Clock and Reset Generator ////
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//// Clock and Reset Generator ////
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//// ////
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//// ////
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//// This file is part of the GPIO project ////
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//// This file is part of the GPIO project ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Clock and reset generator. ////
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//// Clock and reset generator. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/06/05 07:45:21 lampret
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// Revision 1.1 2001/06/05 07:45:21 lampret
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// Added initial RTL and test benches. There are still some issues with these files.
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// Added initial RTL and test benches. There are still some issues with these files.
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module clkrst(clk_o, rst_o);
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module clkrst(clk_o, rst_o);
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//
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//
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// I/O ports
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// I/O ports
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//
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//
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output clk_o; // Clock
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output clk_o; // Clock
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output rst_o; // Reset
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output rst_o; // Reset
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//
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//
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// Internal regs
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// Internal regs
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//
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//
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reg clk_o; // Clock
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reg clk_o; // Clock
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reg rst_o; // Reset
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reg rst_o; // Reset
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initial begin
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initial begin
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clk_o = 0;
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clk_o = 0;
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rst_o = 1;
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rst_o = 1;
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#20;
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#20;
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rst_o = 0;
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rst_o = 0;
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end
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end
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//
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//
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// Clock
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// Clock
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//
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//
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always #4 clk_o = ~clk_o;
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always #4 clk_o = ~clk_o;
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endmodule
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endmodule
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