//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// GPIO Testbench Top ////
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//// GPIO Testbench Top ////
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//// ////
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//// ////
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//// This file is part of the GPIO project ////
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//// This file is part of the GPIO project ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Top level of testbench. It instantiates all blocks. ////
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//// Top level of testbench. It instantiates all blocks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2003/12/17 13:00:14 gorand
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// Revision 1.2 2003/12/17 13:00:14 gorand
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// added ECLK and NEC registers, all tests passed.
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// added ECLK and NEC registers, all tests passed.
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//
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//
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// Revision 1.1 2003/11/30 12:28:19 gorand
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// Revision 1.1 2003/11/30 12:28:19 gorand
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// small "names" modification...
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// small "names" modification...
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//
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//
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// Revision 1.5 2003/11/29 16:22:05 gorand
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// Revision 1.5 2003/11/29 16:22:05 gorand
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// small changes, for VATS...
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// small changes, for VATS...
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//
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//
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// Revision 1.4 2003/11/10 23:23:57 gorand
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// Revision 1.4 2003/11/10 23:23:57 gorand
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// tests passed.
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// tests passed.
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//
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//
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// Revision 1.3 2002/03/13 20:56:16 lampret
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// Revision 1.3 2002/03/13 20:56:16 lampret
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// Removed zero padding as per Avi Shamli suggestion.
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// Removed zero padding as per Avi Shamli suggestion.
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//
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//
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// Revision 1.2 2001/09/18 15:43:28 lampret
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// Revision 1.2 2001/09/18 15:43:28 lampret
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// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:27 lampret
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// Revision 1.1 2001/08/21 21:39:27 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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//
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//
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// Revision 1.2 2001/07/14 20:37:24 lampret
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// Revision 1.2 2001/07/14 20:37:24 lampret
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// Test bench improvements.
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// Test bench improvements.
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//
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//
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// Revision 1.1 2001/06/05 07:45:22 lampret
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// Revision 1.1 2001/06/05 07:45:22 lampret
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// Added initial RTL and test benches. There are still some issues with these files.
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// Added initial RTL and test benches. There are still some issues with these files.
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "gpio_defines.v"
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`include "gpio_defines.v"
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module gpio_testbench();
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module gpio_testbench();
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parameter aw = `GPIO_ADDRHH+1 ;
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parameter aw = `GPIO_ADDRHH+1 ;
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parameter dw = 32;
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parameter dw = 32;
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parameter gw = `GPIO_IOS;
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parameter gw = `GPIO_IOS;
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//
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//
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// Interconnect wires
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// Interconnect wires
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//
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//
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wire clk; // Clock
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wire clk; // Clock
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wire rst; // Reset
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wire rst; // Reset
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wire cyc; // Cycle valid
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wire cyc; // Cycle valid
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wire [aw-1:0] adr; // Address bus
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wire [aw-1:0] adr; // Address bus
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wire [dw-1:0] dat_m; // Data bus from PTC to WBM
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wire [dw-1:0] dat_m; // Data bus from PTC to WBM
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wire [3:0] sel; // Data selects
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wire [3:0] sel; // Data selects
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wire we; // Write enable
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wire we; // Write enable
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wire stb; // Strobe
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wire stb; // Strobe
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wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC
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wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC
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wire ack; // Successful cycle termination
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wire ack; // Successful cycle termination
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wire err; // Failed cycle termination
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wire err; // Failed cycle termination
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wire [gw-1:0] gpio_aux; // GPIO auxiliary signals
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wire [gw-1:0] gpio_aux; // GPIO auxiliary signals
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wire [gw-1:0] gpio_in; // GPIO inputs
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wire [gw-1:0] gpio_in; // GPIO inputs
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wire gpio_eclk; // GPIO external clock
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wire gpio_eclk; // GPIO external clock
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wire [gw-1:0] gpio_out; // GPIO outputs
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wire [gw-1:0] gpio_out; // GPIO outputs
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wire [gw-1:0] gpio_oen; // GPIO output enables
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wire [gw-1:0] gpio_oen; // GPIO output enables
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wire [ 3 : 0] tag_o ;
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wire [ 3 : 0] tag_o ;
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//
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//
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// description of current test.
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// description of current test.
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//
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//
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reg [127:0] text;
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reg [127:0] text;
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//
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//
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// Instantiation of Clock/Reset Generator
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// Instantiation of Clock/Reset Generator
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//
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//
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clkrst clkrst(
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clkrst clkrst(
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// Clock
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// Clock
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.clk_o(clk),
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.clk_o(clk),
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// Reset
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// Reset
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.rst_o(rst)
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.rst_o(rst)
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);
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);
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//
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//
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// Instantiation of Master WISHBONE BFM
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// Instantiation of Master WISHBONE BFM
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//
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//
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wb_master wb_master(
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wb_master wb_master(
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// WISHBONE Interface
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// WISHBONE Interface
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.CLK_I(clk),
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.CLK_I(clk),
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.RST_I(rst),
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.RST_I(rst),
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.CYC_O(cyc),
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.CYC_O(cyc),
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.ADR_O(adr),
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.ADR_O(adr),
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.DAT_O(dat_ptc),
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.DAT_O(dat_ptc),
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.SEL_O(sel),
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.SEL_O(sel),
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.WE_O(we),
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.WE_O(we),
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.STB_O(stb),
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.STB_O(stb),
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.DAT_I(dat_m),
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.DAT_I(dat_m),
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.ACK_I(ack),
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.ACK_I(ack),
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.ERR_I(err),
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.ERR_I(err),
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.RTY_I(1'b0),
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.RTY_I(1'b0),
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.TAG_I(4'b0),
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.TAG_I(4'b0),
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.TAG_O ( tag_o )
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.TAG_O ( tag_o )
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);
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);
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//
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//
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// Instantiation of PTC core
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// Instantiation of PTC core
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//
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//
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gpio_top gpio_top(
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gpio_top gpio_top(
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// WISHBONE Interface
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// WISHBONE Interface
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.wb_clk_i(clk),
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.wb_clk_i(clk),
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.wb_rst_i(rst),
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.wb_rst_i(rst),
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.wb_cyc_i(cyc),
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.wb_cyc_i(cyc),
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.wb_adr_i(adr),
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.wb_adr_i(adr),
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.wb_dat_i(dat_ptc),
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.wb_dat_i(dat_ptc),
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.wb_sel_i(sel),
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.wb_sel_i(sel),
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.wb_we_i(we),
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.wb_we_i(we),
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.wb_stb_i(stb),
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.wb_stb_i(stb),
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.wb_dat_o(dat_m),
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.wb_dat_o(dat_m),
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.wb_ack_o(ack),
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.wb_ack_o(ack),
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.wb_err_o(err),
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.wb_err_o(err),
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.wb_inta_o(),
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.wb_inta_o(),
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// Auxiliary inputs interface
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// Auxiliary inputs interface
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`ifdef GPIO_AUX_IMPLEMENT
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`ifdef GPIO_AUX_IMPLEMENT
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.aux_i(gpio_aux),
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.aux_i(gpio_aux),
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`endif // GPIO_AUX_IMPLEMENT
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`endif // GPIO_AUX_IMPLEMENT
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// External GPIO Interface
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// External GPIO Interface
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.ext_pad_i(gpio_in),
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.ext_pad_i(gpio_in),
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`ifdef GPIO_CLKPAD
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`ifdef GPIO_CLKPAD
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.clk_pad_i(gpio_eclk),
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.clk_pad_i(gpio_eclk),
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`endif // GPIO_CLKPAD
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`endif // GPIO_CLKPAD
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.ext_pad_o(gpio_out),
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.ext_pad_o(gpio_out),
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.ext_padoe_o(gpio_oen)
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.ext_padoe_o(gpio_oen)
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);
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);
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//
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//
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// GPIO Monitor
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// GPIO Monitor
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//
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//
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gpio_mon gpio_mon(
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gpio_mon gpio_mon(
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.gpio_aux(gpio_aux),
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.gpio_aux(gpio_aux),
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.gpio_in(gpio_in),
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.gpio_in(gpio_in),
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.gpio_eclk(gpio_eclk),
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.gpio_eclk(gpio_eclk),
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.gpio_out(gpio_out),
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.gpio_out(gpio_out),
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.gpio_oen(gpio_oen)
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.gpio_oen(gpio_oen)
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);
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);
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initial
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initial
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text = " ";
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text = " ";
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endmodule
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endmodule
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