//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// GPIO Testbench Tasks ////
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//// GPIO Testbench Tasks ////
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//// ////
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//// ////
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//// This file is part of the GPIO project ////
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//// This file is part of the GPIO project ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// http://www.opencores.org/cores/gpio/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Testbench tasks. ////
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//// Testbench tasks. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Nothing ////
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//// Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
|
// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/12/17 13:00:14 gorand
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// Revision 1.10 2003/12/17 13:00:14 gorand
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// added ECLK and NEC registers, all tests passed.
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// added ECLK and NEC registers, all tests passed.
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//
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//
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// Revision 1.9 2003/11/30 12:28:19 gorand
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// Revision 1.9 2003/11/30 12:28:19 gorand
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// small "names" modification...
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// small "names" modification...
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//
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//
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// Revision 1.8 2003/11/19 14:22:43 gorand
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// Revision 1.8 2003/11/19 14:22:43 gorand
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// small changes, to satisfy VATS..
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// small changes, to satisfy VATS..
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//
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//
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// Revision 1.7 2003/11/10 23:23:57 gorand
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// Revision 1.7 2003/11/10 23:23:57 gorand
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// tests passed.
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// tests passed.
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//
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//
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// Revision 1.6 2001/12/25 17:21:06 lampret
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// Revision 1.6 2001/12/25 17:21:06 lampret
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// Fixed two typos.
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// Fixed two typos.
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//
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//
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// Revision 1.5 2001/12/25 17:12:28 lampret
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// Revision 1.5 2001/12/25 17:12:28 lampret
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// Added RGPIO_INTS.
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// Added RGPIO_INTS.
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//
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//
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// Revision 1.4 2001/11/15 02:26:32 lampret
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// Revision 1.4 2001/11/15 02:26:32 lampret
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// Updated timing and fixed some typing errors.
|
// Updated timing and fixed some typing errors.
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//
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//
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// Revision 1.3 2001/09/18 16:37:55 lampret
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// Revision 1.3 2001/09/18 16:37:55 lampret
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// Changed VCD output location.
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// Changed VCD output location.
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//
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//
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// Revision 1.2 2001/09/18 15:43:27 lampret
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// Revision 1.2 2001/09/18 15:43:27 lampret
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// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
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// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
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//
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//
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// Revision 1.1 2001/08/21 21:39:27 lampret
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// Revision 1.1 2001/08/21 21:39:27 lampret
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// Changed directory structure, port names and drfines.
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// Changed directory structure, port names and drfines.
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//
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//
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// Revision 1.2 2001/07/14 20:37:23 lampret
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// Revision 1.2 2001/07/14 20:37:23 lampret
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// Test bench improvements.
|
// Test bench improvements.
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//
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//
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// Revision 1.1 2001/06/05 07:45:22 lampret
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// Revision 1.1 2001/06/05 07:45:22 lampret
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// Added initial RTL and test benches. There are still some issues with these files.
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// Added initial RTL and test benches. There are still some issues with these files.
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//
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//
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//
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//
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|
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`include "timescale.v"
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`include "timescale.v"
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`include "gpio_defines.v"
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`include "gpio_defines.v"
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`include "tb_defines.v"
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`include "tb_defines.v"
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module tb_tasks;
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module tb_tasks;
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integer nr_failed;
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integer nr_failed;
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integer ints_disabled;
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integer ints_disabled;
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integer ints_working;
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integer ints_working;
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integer local_errs;
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integer local_errs;
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parameter sh_addr = `GPIO_ADDRLH+1;
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parameter sh_addr = `GPIO_ADDRLH+1;
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parameter gw = `GPIO_IOS ;
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parameter gw = `GPIO_IOS ;
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//
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//
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// Count/report failed tests
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// Count/report failed tests
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//
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//
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task failed;
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task failed;
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begin
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begin
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$display("FAILED !!!");
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$display("FAILED !!!");
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nr_failed = nr_failed + 1;
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nr_failed = nr_failed + 1;
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end
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end
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endtask
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endtask
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//
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//
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// Set RGPIO_OUT register
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// Set RGPIO_OUT register
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//
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//
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task setout;
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task setout;
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input [31:0] val;
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input [31:0] val;
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reg [ 31:0 ] addr ;
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reg [ 31:0 ] addr ;
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begin
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begin
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addr = `GPIO_RGPIO_OUT <<sh_addr ;
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addr = `GPIO_RGPIO_OUT <<sh_addr ;
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
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/* $display ( " addr : %h %h", addr, val ) ;
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/* $display ( " addr : %h %h", addr, val ) ;
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$display ( " out_pad : %h ", gpio_testbench.gpio_top.out_pad ) ;
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$display ( " out_pad : %h ", gpio_testbench.gpio_top.out_pad ) ;
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$display ( " rgpio_aux : %h ", gpio_testbench.gpio_top.rgpio_aux) ;
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$display ( " rgpio_aux : %h ", gpio_testbench.gpio_top.rgpio_aux) ;
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$display ( " aux_i : %h ", gpio_testbench.gpio_top.aux_i ) ;
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$display ( " aux_i : %h ", gpio_testbench.gpio_top.aux_i ) ;
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$display ( " rgpio_out : %h ", gpio_testbench.gpio_top.rgpio_out ) ;
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$display ( " rgpio_out : %h ", gpio_testbench.gpio_top.rgpio_out ) ;
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*/
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*/
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end
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end
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|
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endtask
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endtask
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|
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//
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//
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// Set RGPIO_OE register
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// Set RGPIO_OE register
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//
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//
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task setoe;
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task setoe;
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input [31:0] val;
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input [31:0] val;
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|
|
begin
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begin
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
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end
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end
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|
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endtask
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endtask
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|
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//
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//
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// Set RGPIO_INTE register
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// Set RGPIO_INTE register
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//
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//
|
task setinte;
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task setinte;
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input [31:0] val;
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input [31:0] val;
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|
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begin
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begin
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
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end
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end
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|
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endtask
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endtask
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|
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//
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//
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// Set RGPIO_PTRIG register
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// Set RGPIO_PTRIG register
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//
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//
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task setptrig;
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task setptrig;
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input [31:0] val;
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input [31:0] val;
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|
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begin
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begin
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
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end
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end
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|
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endtask
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endtask
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|
|
//
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//
|
// Set RGPIO_AUX register
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// Set RGPIO_AUX register
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//
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//
|
task setaux;
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task setaux;
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input [31:0] val;
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input [31:0] val;
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|
|
begin
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begin
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`ifdef GPIO_RGPIO_AUX
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`ifdef GPIO_RGPIO_AUX
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
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`endif // GPIO_RGPIO_AUX
|
`endif // GPIO_RGPIO_AUX
|
end
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end
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|
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endtask
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endtask
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|
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//
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//
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// Set RGPIO_CTRL register
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// Set RGPIO_CTRL register
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//
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//
|
task setctrl;
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task setctrl;
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input [31:0] val;
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input [31:0] val;
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|
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begin
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begin
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
|
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
|
end
|
end
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|
|
endtask
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endtask
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|
|
//
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//
|
// Set RGPIO_INTS register
|
// Set RGPIO_INTS register
|
//
|
//
|
task setints;
|
task setints;
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input [31:0] val;
|
input [31:0] val;
|
|
|
begin
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begin
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111);
|
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111);
|
end
|
end
|
|
|
endtask
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endtask
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|
|
//
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//
|
// Set RGPIO_ECLK register
|
// Set RGPIO_ECLK register
|
//
|
//
|
task seteclk;
|
task seteclk;
|
input [31:0] val;
|
input [31:0] val;
|
|
|
begin
|
begin
|
`ifdef GPIO_RGPIO_ECLK
|
`ifdef GPIO_RGPIO_ECLK
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_ECLK<<sh_addr, val, 4'b1111);
|
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_ECLK<<sh_addr, val, 4'b1111);
|
`endif // GPIO_RGPIO_ECLK
|
`endif // GPIO_RGPIO_ECLK
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Set RGPIO_NEC register
|
// Set RGPIO_NEC register
|
//
|
//
|
task setnec;
|
task setnec;
|
input [31:0] val;
|
input [31:0] val;
|
|
|
begin
|
begin
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`ifdef GPIO_RGPIO_NEC
|
`ifdef GPIO_RGPIO_NEC
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#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_NEC<<sh_addr, val, 4'b1111);
|
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_NEC<<sh_addr, val, 4'b1111);
|
`endif // GPIO_RGPIO_NEC
|
`endif // GPIO_RGPIO_NEC
|
end
|
end
|
|
|
endtask
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endtask
|
|
|
// Display RGPIO_IN register
|
// Display RGPIO_IN register
|
//
|
//
|
task showin;
|
task showin;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
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begin
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#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
|
$write(" RGPIO_IN: %h", tmp);
|
$write(" RGPIO_IN: %h", tmp);
|
end
|
end
|
|
|
endtask
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endtask
|
|
|
//
|
//
|
// Display RGPIO_OUT register
|
// Display RGPIO_OUT register
|
//
|
//
|
task showout;
|
task showout;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
|
$write(" RGPIO_OUT: %h", tmp);
|
$write(" RGPIO_OUT: %h", tmp);
|
end
|
end
|
|
|
endtask
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endtask
|
|
|
|
|
//
|
//
|
// Display RGPIO_OE register
|
// Display RGPIO_OE register
|
//
|
//
|
task showoe;
|
task showoe;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
|
$write(" RGPIO_OE:%h", tmp);
|
$write(" RGPIO_OE:%h", tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_INTE register
|
// Display RGPIO_INTE register
|
//
|
//
|
task showinte;
|
task showinte;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
|
$write(" RGPIO_INTE:%h", tmp);
|
$write(" RGPIO_INTE:%h", tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_PTRIG register
|
// Display RGPIO_PTRIG register
|
//
|
//
|
task showptrig;
|
task showptrig;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
|
$write(" RGPIO_PTRIG:%h", tmp);
|
$write(" RGPIO_PTRIG:%h", tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_AUX register
|
// Display RGPIO_AUX register
|
//
|
//
|
task showaux;
|
task showaux;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
`ifdef GPIO_RGPIO_AUX
|
`ifdef GPIO_RGPIO_AUX
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
|
$write(" RGPIO_AUX:%h", tmp);
|
$write(" RGPIO_AUX:%h", tmp);
|
`endif // GPIO_RGPIO_AUX
|
`endif // GPIO_RGPIO_AUX
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_CTRL register
|
// Display RGPIO_CTRL register
|
//
|
//
|
task showctrl;
|
task showctrl;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
|
$write(" RGPIO_CTRL: %h", tmp);
|
$write(" RGPIO_CTRL: %h", tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_INTS register
|
// Display RGPIO_INTS register
|
//
|
//
|
task showints;
|
task showints;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
|
$write(" RGPIO_INTS:%h", tmp);
|
$write(" RGPIO_INTS:%h", tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_ECLK register
|
// Display RGPIO_ECLK register
|
//
|
//
|
task showeclk;
|
task showeclk;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
`ifdef GPIO_RGPIO_ECLK
|
`ifdef GPIO_RGPIO_ECLK
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp);
|
$write(" RGPIO_ECLK:%h", tmp);
|
$write(" RGPIO_ECLK:%h", tmp);
|
`endif // GPIO_RGPIO_ECLK
|
`endif // GPIO_RGPIO_ECLK
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Display RGPIO_NEC register
|
// Display RGPIO_NEC register
|
//
|
//
|
task shownec;
|
task shownec;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
begin
|
begin
|
`ifdef GPIO_RGPIO_NEC
|
`ifdef GPIO_RGPIO_NEC
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp);
|
$write(" RGPIO_NEC:%h", tmp);
|
$write(" RGPIO_NEC:%h", tmp);
|
`endif // GPIO_RGPIO_NEC
|
`endif // GPIO_RGPIO_NEC
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
|
|
//
|
//
|
// Compare parameter with RGPIO_IN register
|
// Compare parameter with RGPIO_IN register
|
//
|
//
|
task comp_in;
|
task comp_in;
|
input [31:0] val;
|
input [31:0] val;
|
output ret;
|
output ret;
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
reg ret;
|
reg ret;
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
|
|
|
if (tmp == val)
|
if (tmp == val)
|
ret = 1;
|
ret = 1;
|
else
|
else
|
ret = 0;
|
ret = 0;
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_IN register
|
// Get RGPIO_IN register
|
//
|
//
|
task getin;
|
task getin;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_OUT register
|
// Get RGPIO_OUT register
|
//
|
//
|
task getout;
|
task getout;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_OE register
|
// Get RGPIO_OE register
|
//
|
//
|
task getoe;
|
task getoe;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_INTE register
|
// Get RGPIO_INTE register
|
//
|
//
|
task getinte;
|
task getinte;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_PTRIG register
|
// Get RGPIO_PTRIG register
|
//
|
//
|
task getptrig;
|
task getptrig;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_AUX register
|
// Get RGPIO_AUX register
|
//
|
//
|
task getaux;
|
task getaux;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
`ifdef GPIO_RGPIO_AUX
|
`ifdef GPIO_RGPIO_AUX
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
|
`endif // GPIO_RGPIO_AUX
|
`endif // GPIO_RGPIO_AUX
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_CTRL register
|
// Get RGPIO_CTRL register
|
//
|
//
|
task getctrl;
|
task getctrl;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_INTS register
|
// Get RGPIO_INTS register
|
//
|
//
|
task getints;
|
task getints;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_ECLK register
|
// Get RGPIO_ECLK register
|
//
|
//
|
task geteclk;
|
task geteclk;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
`ifdef GPIO_RGPIO_ECLK
|
`ifdef GPIO_RGPIO_ECLK
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp);
|
`endif // GPIO_RGPIO_ECLK
|
`endif // GPIO_RGPIO_ECLK
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Get RGPIO_NEC register
|
// Get RGPIO_NEC register
|
//
|
//
|
task getnec;
|
task getnec;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
`ifdef GPIO_RGPIO_NEC
|
`ifdef GPIO_RGPIO_NEC
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp);
|
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp);
|
`endif // GPIO_RGPIO_NEC
|
`endif // GPIO_RGPIO_NEC
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Calculate a random and make it narrow to fit on GPIO I/O pins
|
// Calculate a random and make it narrow to fit on GPIO I/O pins
|
//
|
//
|
task random_gpio;
|
task random_gpio;
|
output [31:0] tmp;
|
output [31:0] tmp;
|
|
|
begin
|
begin
|
tmp = $random & ((1<<`GPIO_IOS)-1);
|
tmp = $random & ((1<<`GPIO_IOS)-1);
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//
|
//
|
// Test operation of control bit RGPIO_CTRL[ECLK]
|
// Test operation of control bit RGPIO_CTRL[ECLK]
|
//
|
//
|
task test_eclk;
|
task test_eclk;
|
reg [gw-1:0 ] l1, l2, l3;
|
reg [gw-1:0 ] l1, l2, l3;
|
reg [gw-1:0 ] r1, r2, r3;
|
reg [gw-1:0 ] r1, r2, r3;
|
begin
|
begin
|
|
|
// Set external clock to low state
|
// Set external clock to low state
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
//
|
//
|
// Phase 1
|
// Phase 1
|
//
|
//
|
// GPIO uses WISHBONE clock to latch gpio_in
|
// GPIO uses WISHBONE clock to latch gpio_in
|
//
|
//
|
|
|
// Put something on gpio_in pins
|
// Put something on gpio_in pins
|
random_gpio(r1);
|
random_gpio(r1);
|
gpio_testbench.gpio_mon.set_gpioin(r1);
|
gpio_testbench.gpio_mon.set_gpioin(r1);
|
|
|
// Reset GPIO_CTRL
|
// Reset GPIO_CTRL
|
setctrl(0);
|
setctrl(0);
|
seteclk ( 32'h00000000 ) ;
|
seteclk ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
|
|
// Wait for time to advance
|
// Wait for time to advance
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read GPIO_RGPIO_IN
|
// Read GPIO_RGPIO_IN
|
getin(l1);
|
getin(l1);
|
|
|
//
|
//
|
// Phase 2
|
// Phase 2
|
//
|
//
|
// GPIO uses external clock to latch gpio_in
|
// GPIO uses external clock to latch gpio_in
|
//
|
//
|
|
|
// Set GPIO to use external clock, NEC bit cleared
|
// Set GPIO to use external clock, NEC bit cleared
|
//setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
|
//setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
|
seteclk ( 32'hffffffff ) ;
|
seteclk ( 32'hffffffff ) ;
|
setnec ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
// Put something else on gpio_in pins
|
// Put something else on gpio_in pins
|
random_gpio(r2);
|
random_gpio(r2);
|
gpio_testbench.gpio_mon.set_gpioin(r2);
|
gpio_testbench.gpio_mon.set_gpioin(r2);
|
|
|
// Make an external posedge clock pulse
|
// Make an external posedge clock pulse
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read RGPIO_IN
|
// Read RGPIO_IN
|
getin(l2);
|
getin(l2);
|
|
|
//
|
//
|
// Phase 3
|
// Phase 3
|
//
|
//
|
// Change GPIO inputs and WB clock but not external clock.
|
// Change GPIO inputs and WB clock but not external clock.
|
// RGPIO_IN should not change.
|
// RGPIO_IN should not change.
|
//
|
//
|
|
|
// Put something else on gpio_in pins
|
// Put something else on gpio_in pins
|
random_gpio(r3);
|
random_gpio(r3);
|
gpio_testbench.gpio_mon.set_gpioin(r3);
|
gpio_testbench.gpio_mon.set_gpioin(r3);
|
|
|
// Wait for WB clock
|
// Wait for WB clock
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read RGPIO_IN
|
// Read RGPIO_IN
|
getin(l3);
|
getin(l3);
|
|
|
//
|
//
|
// Phase 4
|
// Phase 4
|
//
|
//
|
// Compare phases
|
// Compare phases
|
//
|
//
|
//$display ( "data : " ) ;
|
//$display ( "data : " ) ;
|
//$display ( " l1 = %h r1 = %h l2 = %h r2 = %h l3 = %h ", l1,r1,l2,r2,l3);
|
//$display ( " l1 = %h r1 = %h l2 = %h r2 = %h l3 = %h ", l1,r1,l2,r2,l3);
|
if (l1 == r1 && l2 == r2 && l2 == l3)
|
if (l1 == r1 && l2 == r2 && l2 == l3)
|
$write(".");
|
$write(".");
|
else
|
else
|
local_errs = local_errs + 1;
|
local_errs = local_errs + 1;
|
end
|
end
|
endtask
|
endtask
|
|
|
//
|
//
|
// Test operation of control bit RGPIO_CTRL[NEC]
|
// Test operation of control bit RGPIO_CTRL[NEC]
|
//
|
//
|
task test_nec;
|
task test_nec;
|
integer l1, l2;
|
integer l1, l2;
|
integer r1, r2;
|
integer r1, r2;
|
begin
|
begin
|
//
|
//
|
// Phase 1
|
// Phase 1
|
//
|
//
|
// Compare RGPIO_IN before and after negative edge
|
// Compare RGPIO_IN before and after negative edge
|
//
|
//
|
|
|
// Set external clock to low state
|
// Set external clock to low state
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Set GPIO to use external clock and set RGPIO_CTRL[NEC]
|
// Set GPIO to use external clock and set RGPIO_CTRL[NEC]
|
//setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
|
//setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
|
seteclk ( 32'hffffffff ) ;
|
seteclk ( 32'hffffffff ) ;
|
setnec ( 32'hffffffff ) ;
|
setnec ( 32'hffffffff ) ;
|
// Put random on gpio inputs
|
// Put random on gpio inputs
|
random_gpio(r1);
|
random_gpio(r1);
|
gpio_testbench.gpio_mon.set_gpioin(r1);
|
gpio_testbench.gpio_mon.set_gpioin(r1);
|
|
|
// Advance time by making an external negedge clock pulse
|
// Advance time by making an external negedge clock pulse
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Put something on gpio_in pins
|
// Put something on gpio_in pins
|
random_gpio(r2);
|
random_gpio(r2);
|
gpio_testbench.gpio_mon.set_gpioin(r2);
|
gpio_testbench.gpio_mon.set_gpioin(r2);
|
|
|
// Make an external posedge clock pulse
|
// Make an external posedge clock pulse
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read RGPIO_IN (should be the same as r1)
|
// Read RGPIO_IN (should be the same as r1)
|
getin(l1);
|
getin(l1);
|
|
|
// Make an external negedge clock pulse
|
// Make an external negedge clock pulse
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
gpio_testbench.gpio_mon.set_gpioeclk(1);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read RGPIO_IN (should be the same as r2)
|
// Read RGPIO_IN (should be the same as r2)
|
getin(l2);
|
getin(l2);
|
|
|
//
|
//
|
// Phase 2
|
// Phase 2
|
//
|
//
|
// Compare phases
|
// Compare phases
|
//
|
//
|
// $display("l1 %h l2 %h r1 %h r2 %h", l1, l2, r1, r2);
|
// $display("l1 %h l2 %h r1 %h r2 %h", l1, l2, r1, r2);
|
if (l1 == r1 && l2 == r2)
|
if (l1 == r1 && l2 == r2)
|
$write(".");
|
$write(".");
|
else
|
else
|
local_errs = local_errs + 1;
|
local_errs = local_errs + 1;
|
end
|
end
|
endtask
|
endtask
|
|
|
//
|
//
|
// Test input polled mode, output mode and bidirectional
|
// Test input polled mode, output mode and bidirectional
|
//
|
//
|
task test_simple;
|
task test_simple;
|
reg [gw-1:0] l1, l2, l3, l4;
|
reg [gw-1:0] l1, l2, l3, l4;
|
integer i, err;
|
integer i, err;
|
begin
|
begin
|
$write(" Testing input mode ...");
|
$write(" Testing input mode ...");
|
|
|
//
|
//
|
// Phase 1
|
// Phase 1
|
//
|
//
|
// Compare RGPIO_IN and gpio_in
|
// Compare RGPIO_IN and gpio_in
|
//
|
//
|
|
|
// Set GPIO to use WB clock
|
// Set GPIO to use WB clock
|
setctrl(0);
|
setctrl(0);
|
seteclk ( 32'h00000000 ) ;
|
seteclk ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
|
|
err = 0;
|
err = 0;
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
// Put something on gpio_in pins
|
// Put something on gpio_in pins
|
random_gpio(l1);
|
random_gpio(l1);
|
gpio_testbench.gpio_mon.set_gpioin(l1);
|
gpio_testbench.gpio_mon.set_gpioin(l1);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read GPIO_RGPIO_IN
|
// Read GPIO_RGPIO_IN
|
getin(l2);
|
getin(l2);
|
|
|
// Compare gpio_in and RGPIO_IN. Should be equal.
|
// Compare gpio_in and RGPIO_IN. Should be equal.
|
if (l1 != l2)
|
if (l1 != l2)
|
err = err + 1;
|
err = err + 1;
|
end
|
end
|
|
|
// Phase 2
|
// Phase 2
|
//
|
//
|
// Output result for previous test
|
// Output result for previous test
|
//
|
//
|
if (!err)
|
if (!err)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
|
|
$write(" Testing output mode ...");
|
$write(" Testing output mode ...");
|
|
|
//
|
//
|
// Phase 3
|
// Phase 3
|
//
|
//
|
// Compare RGPIO_OUT and gpio_out
|
// Compare RGPIO_OUT and gpio_out
|
//
|
//
|
|
|
err = 0;
|
err = 0;
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
// Put something in RGPIO_OUT pins
|
// Put something in RGPIO_OUT pins
|
l1 = $random;
|
l1 = $random;
|
setout(l1);
|
setout(l1);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read gpio_out
|
// Read gpio_out
|
gpio_testbench.gpio_mon.get_gpioout(l2);
|
gpio_testbench.gpio_mon.get_gpioout(l2);
|
|
|
// Compare gpio_out and RGPIO_OUT. Should be equal.
|
// Compare gpio_out and RGPIO_OUT. Should be equal.
|
if (l1 != l2)
|
if (l1 != l2)
|
err = err + 1;
|
err = err + 1;
|
end
|
end
|
|
|
// Phase 4
|
// Phase 4
|
//
|
//
|
// Output result for previous test
|
// Output result for previous test
|
//
|
//
|
if (!err)
|
if (!err)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
|
|
$write(" Testing bidirectional I/O ...");
|
$write(" Testing bidirectional I/O ...");
|
|
|
//
|
//
|
// Phase 5
|
// Phase 5
|
//
|
//
|
// Compare RGPIO_OE and gpio_oen
|
// Compare RGPIO_OE and gpio_oen
|
//
|
//
|
|
|
err = 0;
|
err = 0;
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
// Put something in RGPIO_OE pins
|
// Put something in RGPIO_OE pins
|
l1 = $random;
|
l1 = $random;
|
setoe(l1);
|
setoe(l1);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read gpio_oen
|
// Read gpio_oen
|
gpio_testbench.gpio_mon.get_gpiooen(l2);
|
gpio_testbench.gpio_mon.get_gpiooen(l2);
|
|
|
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
|
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
|
if (l1 != l2)
|
if (l1 != l2)
|
err = err + 1;
|
err = err + 1;
|
end
|
end
|
|
|
// Phase 6
|
// Phase 6
|
//
|
//
|
// Output result for previous test
|
// Output result for previous test
|
//
|
//
|
if (!err)
|
if (!err)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
|
|
$write(" Testing auxiliary feature ...");
|
$write(" Testing auxiliary feature ...");
|
`ifdef GPIO_AUX_IMPLEMENT
|
`ifdef GPIO_AUX_IMPLEMENT
|
//
|
//
|
// Phase 7
|
// Phase 7
|
//
|
//
|
// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
|
// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
|
//
|
//
|
|
|
err = 0;
|
err = 0;
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
|
// Put something on gpio_aux pins
|
// Put something on gpio_aux pins
|
l1 = $random;
|
l1 = $random;
|
gpio_testbench.gpio_mon.set_gpioaux(l1);
|
gpio_testbench.gpio_mon.set_gpioaux(l1);
|
|
|
// Put something in RGPIO_AUX pins
|
// Put something in RGPIO_AUX pins
|
l2 = $random;
|
l2 = $random;
|
setaux(l2);
|
setaux(l2);
|
|
|
// Put something in RGPIO_OUT pins
|
// Put something in RGPIO_OUT pins
|
l3 = $random;
|
l3 = $random;
|
setout(l3);
|
setout(l3);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Read gpio_out
|
// Read gpio_out
|
gpio_testbench.gpio_mon.get_gpioout(l4);
|
gpio_testbench.gpio_mon.get_gpioout(l4);
|
|
|
// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
|
// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
|
// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT
|
// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT
|
// bits are present on gpio_out and where
|
// bits are present on gpio_out and where
|
if ((l1 & l2 | l3 & ~l2) != l4)
|
if ((l1 & l2 | l3 & ~l2) != l4)
|
err = err + 1;
|
err = err + 1;
|
end
|
end
|
|
|
// Phase 8
|
// Phase 8
|
//
|
//
|
// Output result for previous test
|
// Output result for previous test
|
//
|
//
|
if (!err)
|
if (!err)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
|
|
`else
|
`else
|
$display(" Not implemented !!");
|
$display(" Not implemented !!");
|
`endif // GPIO_AUX_IMPLEMENT
|
`endif // GPIO_AUX_IMPLEMENT
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
//
|
//
|
// Test interrupts
|
// Test interrupts
|
//
|
//
|
task test_ints;
|
task test_ints;
|
integer l1, l2, l3, l4;
|
integer l1, l2, l3, l4;
|
integer i, rnd, err;
|
integer i, rnd, err;
|
integer r1;
|
integer r1;
|
begin
|
begin
|
|
|
$write(" Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
|
$write(" Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
|
|
|
//
|
//
|
// Phase 1
|
// Phase 1
|
//
|
//
|
// Generate patterns on inputs in interrupt mode
|
// Generate patterns on inputs in interrupt mode
|
//
|
//
|
|
|
// Disable spurious interrupt monitor
|
// Disable spurious interrupt monitor
|
ints_disabled = 0;
|
ints_disabled = 0;
|
seteclk ( 32'h00000000 ) ;
|
seteclk ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
|
|
err = 0;
|
err = 0;
|
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
|
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
|
|
|
// Set gpio_in pins
|
// Set gpio_in pins
|
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
|
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
|
gpio_testbench.gpio_mon.set_gpioin(r1);
|
gpio_testbench.gpio_mon.set_gpioin(r1);
|
|
|
// Low level triggering
|
// Low level triggering
|
setptrig(0);
|
setptrig(0);
|
|
|
// Clear RGPIO_INTS
|
// Clear RGPIO_INTS
|
setints(0);
|
setints(0);
|
|
|
// Enable interrupts in RGPIO_CTRL
|
// Enable interrupts in RGPIO_CTRL
|
setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
|
setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
|
|
|
// Enable interrupts in RGPIO_INTE
|
// Enable interrupts in RGPIO_INTE
|
setinte(r1);
|
setinte(r1);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Sample interrupt request. Should be zero.
|
// Sample interrupt request. Should be zero.
|
l1 = gpio_testbench.gpio_top.wb_inta_o;
|
l1 = gpio_testbench.gpio_top.wb_inta_o;
|
|
|
// Clear gpio_in pins
|
// Clear gpio_in pins
|
gpio_testbench.gpio_mon.set_gpioin(0);
|
gpio_testbench.gpio_mon.set_gpioin(0);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Sample interrupt request. Should be one.
|
// Sample interrupt request. Should be one.
|
l2 = gpio_testbench.gpio_top.wb_inta_o;
|
l2 = gpio_testbench.gpio_top.wb_inta_o;
|
|
|
// Clear interrupt request
|
// Clear interrupt request
|
setctrl(0);
|
setctrl(0);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Sample interrupt request. Should be zero.
|
// Sample interrupt request. Should be zero.
|
l3 = gpio_testbench.gpio_top.wb_inta_o;
|
l3 = gpio_testbench.gpio_top.wb_inta_o;
|
|
|
// Get RGPIO_INTS. Should be nonzero.
|
// Get RGPIO_INTS. Should be nonzero.
|
getints(l4);
|
getints(l4);
|
|
|
// Check for errors
|
// Check for errors
|
if (l1 || !l2 || l3 || (l4 != r1)) begin
|
if (l1 || !l2 || l3 || (l4 != r1)) begin
|
err = err +1;
|
err = err +1;
|
end
|
end
|
end
|
end
|
|
|
// Enable spurious interrupt monitor
|
// Enable spurious interrupt monitor
|
ints_disabled = 1;
|
ints_disabled = 1;
|
|
|
// Phase 2
|
// Phase 2
|
//
|
//
|
// Check results
|
// Check results
|
//
|
//
|
if (!err)
|
if (!err)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
end
|
end
|
endtask
|
endtask
|
|
|
//
|
//
|
// Test ptrig
|
// Test ptrig
|
//
|
//
|
task test_ptrig;
|
task test_ptrig;
|
integer l1, l2, l3;
|
integer l1, l2, l3;
|
integer i, rnd, err;
|
integer i, rnd, err;
|
integer r1;
|
integer r1;
|
begin
|
begin
|
$write(" Testing ptrig features ...");
|
$write(" Testing ptrig features ...");
|
|
|
//
|
//
|
// Phase 1
|
// Phase 1
|
//
|
//
|
// Generate patterns on inputs in interrupt mode
|
// Generate patterns on inputs in interrupt mode
|
//
|
//
|
|
|
// Disable spurious interrupt monitor
|
// Disable spurious interrupt monitor
|
ints_disabled = 0;
|
ints_disabled = 0;
|
seteclk ( 32'h00000000 ) ;
|
seteclk ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
setnec ( 32'h00000000 ) ;
|
|
|
err = 0;
|
err = 0;
|
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
|
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin
|
|
|
// Set bits to one
|
// Set bits to one
|
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
|
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
|
|
|
// Set gpio_in pins
|
// Set gpio_in pins
|
gpio_testbench.gpio_mon.set_gpioin('h00000000);
|
gpio_testbench.gpio_mon.set_gpioin('h00000000);
|
|
|
// Clear old interrupts
|
// Clear old interrupts
|
setints(0);
|
setints(0);
|
|
|
// High level triggering
|
// High level triggering
|
setptrig('hffffffff);
|
setptrig('hffffffff);
|
|
|
// Enable interrupts in RGPIO_CTRL
|
// Enable interrupts in RGPIO_CTRL
|
setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
|
setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
|
|
|
// Enable interrupts in RGPIO_INTE
|
// Enable interrupts in RGPIO_INTE
|
setinte(r1);
|
setinte(r1);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Sample interrupt request. Should be zero.
|
// Sample interrupt request. Should be zero.
|
l1 = gpio_testbench.gpio_top.wb_inta_o;
|
l1 = gpio_testbench.gpio_top.wb_inta_o;
|
|
|
// Clear gpio_in pins
|
// Clear gpio_in pins
|
gpio_testbench.gpio_mon.set_gpioin('hffffffff);
|
gpio_testbench.gpio_mon.set_gpioin('hffffffff);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Sample interrupt request. Should be one.
|
// Sample interrupt request. Should be one.
|
l2 = gpio_testbench.gpio_top.wb_inta_o;
|
l2 = gpio_testbench.gpio_top.wb_inta_o;
|
|
|
// Clear interrupt request
|
// Clear interrupt request
|
setctrl(0);
|
setctrl(0);
|
setints(0);
|
setints(0);
|
|
|
// Advance time
|
// Advance time
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
@(posedge gpio_testbench.clk);
|
|
|
// Sample interrupt request. Should be zero.
|
// Sample interrupt request. Should be zero.
|
l3 = gpio_testbench.gpio_top.wb_inta_o;
|
l3 = gpio_testbench.gpio_top.wb_inta_o;
|
|
|
// Check for errors
|
// Check for errors
|
if (l1 || !l2 || l3)
|
if (l1 || !l2 || l3)
|
err = err +1;
|
err = err +1;
|
end
|
end
|
|
|
// Enable spurious interrupt monitor
|
// Enable spurious interrupt monitor
|
ints_disabled = 1;
|
ints_disabled = 1;
|
|
|
// Phase 2
|
// Phase 2
|
//
|
//
|
// Check results
|
// Check results
|
//
|
//
|
if (!err)
|
if (!err)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
end
|
end
|
endtask
|
endtask
|
|
|
//
|
//
|
// Do continues check for interrupts
|
// Do continues check for interrupts
|
//
|
//
|
always @(posedge gpio_testbench.gpio_top.wb_inta_o)
|
always @(posedge gpio_testbench.gpio_top.wb_inta_o)
|
if (ints_disabled) begin
|
if (ints_disabled) begin
|
$display("Spurious interrupt detected. ");
|
$display("Spurious interrupt detected. ");
|
failed;
|
failed;
|
ints_working = 9876;
|
ints_working = 9876;
|
$display;
|
$display;
|
end
|
end
|
|
|
//
|
//
|
// Start of testbench test tasks
|
// Start of testbench test tasks
|
//
|
//
|
integer i;
|
integer i;
|
initial begin
|
initial begin
|
`ifdef GPIO_DUMP_VCD
|
`ifdef GPIO_DUMP_VCD
|
$dumpfile("../out/gpio_testbench.vcd");
|
$dumpfile("../out/gpio_testbench.vcd");
|
$dumpvars(0);
|
$dumpvars(0);
|
`endif
|
`endif
|
nr_failed = 0;
|
nr_failed = 0;
|
ints_disabled = 1;
|
ints_disabled = 1;
|
ints_working = 0;
|
ints_working = 0;
|
gpio_testbench.gpio_mon.set_gpioin(0);
|
gpio_testbench.gpio_mon.set_gpioin(0);
|
gpio_testbench.gpio_mon.set_gpioaux(0);
|
gpio_testbench.gpio_mon.set_gpioaux(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
gpio_testbench.gpio_mon.set_gpioeclk(0);
|
$display;
|
$display;
|
$display("###");
|
$display("###");
|
$display("### GPIO IP Core Verification ###");
|
$display("### GPIO IP Core Verification ###");
|
$display("###");
|
$display("###");
|
|
|
`ifdef GPIO_IMPLEMENTED
|
`ifdef GPIO_IMPLEMENTED
|
|
|
$display;
|
$display;
|
$display("I. Testing correct operation of RGPIO_CTRL control bits");
|
$display("I. Testing correct operation of RGPIO_CTRL control bits");
|
$display;
|
$display;
|
|
|
|
|
local_errs = 0;
|
local_errs = 0;
|
#1
|
#1
|
|
|
gpio_testbench.text = "Test INTS";
|
gpio_testbench.text = "Test INTS";
|
test_ints;
|
test_ints;
|
|
|
$display;
|
$display;
|
$display("II. Testing modes of operation ...");
|
$display("II. Testing modes of operation ...");
|
$display;
|
$display;
|
|
|
gpio_testbench.text = "Test simple";
|
gpio_testbench.text = "Test simple";
|
test_simple;
|
test_simple;
|
gpio_testbench.text = "Test ptrig";
|
gpio_testbench.text = "Test ptrig";
|
test_ptrig;
|
test_ptrig;
|
|
|
|
|
$display;
|
$display;
|
$display("III. Testing registers external clock");
|
$display("III. Testing registers external clock");
|
$display;
|
$display;
|
|
|
`ifdef GPIO_CLKPAD
|
`ifdef GPIO_CLKPAD
|
$write(" Testing control register ECLK ...");
|
$write(" Testing control register ECLK ...");
|
gpio_testbench.text = "Test ECLK";
|
gpio_testbench.text = "Test ECLK";
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
|
test_eclk;
|
test_eclk;
|
if (local_errs == 0)
|
if (local_errs == 0)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
|
|
$write(" Testing control register NEC ...");
|
$write(" Testing control register NEC ...");
|
local_errs = 0;
|
local_errs = 0;
|
gpio_testbench.text = "Test NEC";
|
gpio_testbench.text = "Test NEC";
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
|
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1)
|
test_nec;
|
test_nec;
|
if (local_errs == 0)
|
if (local_errs == 0)
|
$display(" OK");
|
$display(" OK");
|
else
|
else
|
failed;
|
failed;
|
`else
|
`else
|
$display(" External clock not enabled!!");
|
$display(" External clock not enabled!!");
|
`endif // GPIO_CLKPAD
|
`endif // GPIO_CLKPAD
|
|
|
$display;
|
$display;
|
$display("###");
|
$display("###");
|
$display("### FAILED TESTS: %d ###", nr_failed);
|
$display("### FAILED TESTS: %d ###", nr_failed);
|
$display("###");
|
$display("###");
|
$display;
|
$display;
|
|
|
`else
|
`else
|
|
|
$display("###");
|
$display("###");
|
$display("### GPIO not implemented ");
|
$display("### GPIO not implemented ");
|
$display("###");
|
$display("###");
|
nr_failed = 1;
|
nr_failed = 1;
|
|
|
`endif // GPIO_IMPLEMENTED
|
`endif // GPIO_IMPLEMENTED
|
// $finish;
|
// $finish;
|
if ( nr_failed == 0 )
|
if ( nr_failed == 0 )
|
begin
|
begin
|
$display ("report (%h)", 32'hdeaddead ) ;
|
$display ("report (%h)", 32'hdeaddead ) ;
|
$display ("exit (00000000)" ) ;
|
$display ("exit (00000000)" ) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display ("report (%h)", 32'heeeeeeee ) ;
|
$display ("report (%h)", 32'heeeeeeee ) ;
|
$display ("exit (00000000)" ) ;
|
$display ("exit (00000000)" ) ;
|
end
|
end
|
$finish(0);
|
$finish(0);
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
