#!/bin/bash
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#!/bin/bash
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#
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#
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# This script runs RTL and gate-level simulation using different simultion tools.
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# This script runs RTL and gate-level simulation using different simultion tools.
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# Right now Cadence Verilog-XL and NCSim are supported.
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# Right now Cadence Verilog-XL and NCSim are supported.
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#
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#
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# Author: Damjan Lampret
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# Author: Damjan Lampret
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#
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#
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#
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#
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# User definitions
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# User definitions
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#
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#
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# Set simulation tool you are using (xl, ncsim, ncver)
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# Set simulation tool you are using (xl, ncsim, ncver)
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SIMTOOL=ncsim
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SIMTOOL=ncsim
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# Set test bench top module(s)
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# Set test bench top module(s)
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TB_TOP="tb_tasks"
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TB_TOP="tb_tasks"
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# Set include directories
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# Set include directories
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INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
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INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
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# Set test bench files
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# Set test bench files
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BENCH_FILES="../../../bench/verilog/*.v"
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BENCH_FILES="../../../bench/verilog/*.v"
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# Set RTL source files
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# Set RTL source files
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RTL_FILES="../../../rtl/verilog/*.v"
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RTL_FILES="../../../rtl/verilog/*.v"
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# Set gate-level netlist files
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# Set gate-level netlist files
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GATE_FILES="../syn/out/final_gpio.v"
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GATE_FILES="../syn/out/final_gpio.v"
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# Set libraries (standard cell etc.)
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# Set libraries (standard cell etc.)
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LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
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LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
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# Set parameters for simulation tool
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# Set parameters for simulation tool
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if [ $SIMTOOL == xl ]; then
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if [ $SIMTOOL == xl ]; then
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PARAM="+turbo+3 -q"
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PARAM="+turbo+3 -q"
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for i in $INCLUDE_DIRS; do
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for i in $INCLUDE_DIRS; do
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INCDIR=$INCDIR" +incdir+$i"
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INCDIR=$INCDIR" +incdir+$i"
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done
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done
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elif [ $SIMTOOL == ncver ]; then
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elif [ $SIMTOOL == ncver ]; then
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NCVER_PARAM=""
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NCVER_PARAM=""
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for i in $INCLUDE_DIRS; do
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for i in $INCLUDE_DIRS; do
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INCDIR=$INCDIR" +incdir+$i"
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INCDIR=$INCDIR" +incdir+$i"
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done
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done
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elif [ $SIMTOOL == ncsim ]; then
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elif [ $SIMTOOL == ncsim ]; then
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NCPREP_PARAM="-UPDATE +overwrite"
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NCPREP_PARAM="-UPDATE +overwrite"
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NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
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NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
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for i in $INCLUDE_DIRS; do
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for i in $INCLUDE_DIRS; do
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INCDIR=$INCDIR" +incdir+$i"
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INCDIR=$INCDIR" +incdir+$i"
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done
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done
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else
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else
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echo "$SIMTOOL is unsupported simulation tool."
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echo "$SIMTOOL is unsupported simulation tool."
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exit 0
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exit 0
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fi
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fi
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#
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#
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# Don't change anything below unless you know what you are doing
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# Don't change anything below unless you know what you are doing
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#
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#
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# Run simulation in sim directory
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# Run simulation in sim directory
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cd ../sim
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#cd ../sim
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# Run actual simulation
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# Run actual simulation
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# Cadence Verilog-XL
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# Cadence Verilog-XL
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if [ $SIMTOOL == xl ]; then
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if [ $SIMTOOL == xl ]; then
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# RTL simulation
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# RTL simulation
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if [ "$1" == rtl ]; then
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if [ "$1" == rtl ]; then
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verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
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verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
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# Gate-level simulation
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# Gate-level simulation
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elif [ "$1" == gate ]; then
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elif [ "$1" == gate ]; then
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verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
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verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
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# Wrong parameter or no parameter
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# Wrong parameter or no parameter
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else
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else
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echo "Usage: $0 [rtl|gate]"
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echo "Usage: $0 [rtl|gate]"
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exit 0
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exit 0
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fi
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fi
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# Cadence Ncverilog
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# Cadence Ncverilog
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elif [ $SIMTOOL == ncver ]; then
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elif [ $SIMTOOL == ncver ]; then
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# RTL simulation
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# RTL simulation
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if [ "$1" == rtl ]; then
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if [ "$1" == rtl ]; then
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ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
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ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
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cp ncverilog.log ../log
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cp ncverilog.log ../log
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# Gate-level simulation
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# Gate-level simulation
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elif [ "$1" == gate ]; then
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elif [ "$1" == gate ]; then
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ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
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ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
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cp ncverilog.log ../log
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cp ncverilog.log ../log
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# Wrong parameter or no parameter
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# Wrong parameter or no parameter
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else
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else
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echo "Usage: $0 [rtl|gate]"
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echo "Usage: $0 [rtl|gate]"
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exit 0
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exit 0
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fi
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fi
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# Cadence Ncsim
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# Cadence Ncsim
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elif [ $SIMTOOL == ncsim ]; then
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elif [ $SIMTOOL == ncsim ]; then
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# RTL simulation
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# RTL simulation
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if [ "$1" == rtl ]; then
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if [ "$1" == rtl ]; then
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ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
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ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
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./RUN_NC
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./RUN_NC
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# Gate-level simulation
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# Gate-level simulation
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elif [ "$1" == gate ]; then
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elif [ "$1" == gate ]; then
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ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
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ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
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./RUN_NC
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./RUN_NC
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# Wrong parameter or no parameter
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# Wrong parameter or no parameter
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else
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else
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echo "Usage: $0 [rtl|gate]"
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echo "Usage: $0 [rtl|gate]"
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exit 0
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exit 0
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fi
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fi
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# Unsupported simulation tool
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# Unsupported simulation tool
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else
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else
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echo "$SIMTOOL is unsupported simulation tool."
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echo "$SIMTOOL is unsupported simulation tool."
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exit 0;
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exit 0;
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fi
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fi
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