/*
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/*
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* wb_slv_wrapper.v
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* wb_slv_wrapper.v
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*
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*
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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* version 2.1 of the License, or (at your option) any later version.
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*
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*
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* This library is distributed in the hope that it will be useful,
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* Lesser General Public License for more details.
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*
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*
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* You should have received a copy of the GNU Lesser General Public
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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* MA 02110-1301 USA
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*/
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*/
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module wb_slv_wrapper (
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module wb_slv_wrapper (
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// wishbone side
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// wishbone side
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input rst_i,clk_i,
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input rst_i,clk_i,
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input stb_i,we_i,
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input stb_i,we_i,
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output ack_o,
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output ack_o,
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input [31:0] adr_i, // in byte
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input [31:0] adr_i, // in byte
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input [31:0] dat_i,
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input [31:0] dat_i,
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output [31:0] dat_o,
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output [31:0] dat_o,
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// localbus side
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// localbus side
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output rst,clk
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output rst,clk,
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output wr_out,rd_out,
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output wr_out,rd_out,
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output [ 7:0] addr_out, // in byte
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output [ 7:0] addr_out, // in byte
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output [31:0] data_out,
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output [31:0] data_out,
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input [31:0] data_in
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input [31:0] data_in
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);
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);
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reg stb_i_d1;
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reg stb_i_d1;
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wire stb_internal = stb_i && !stb_i_d1;
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wire stb_internal = stb_i && !stb_i_d1;
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reg ack_internal;
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reg ack_internal;
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// localbus output
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// localbus output
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always @(posedge rst_i or posedge clk_i) begin
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always @(posedge rst_i or posedge clk_i) begin
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if (rst_i)
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if (rst_i)
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stb_i_d1 <= 1'b0;
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stb_i_d1 <= 1'b0;
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else if (ack_internal)
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else if (ack_internal)
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stb_i_d1 <= 1'b0;
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stb_i_d1 <= 1'b0;
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else
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else
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stb_i_d1 <= stb_i;
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stb_i_d1 <= stb_i;
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end
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end
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assign {rst, clk} = {rst_i, clk_i};
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assign {rst, clk} = {rst_i, clk_i};
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assign wr_out = stb_internal && we_i;
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assign wr_out = stb_internal && we_i;
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assign rd_out = stb_internal && !we_i;
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assign rd_out = stb_internal && !we_i;
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assign addr_out[ 7:0] = adr_i[ 7:0];
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assign addr_out[ 7:0] = adr_i[ 7:0];
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assign data_out[31:0] = dat_i[31:0];
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assign data_out[31:0] = dat_i[31:0];
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// wishbone output
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// wishbone output
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always @(posedge rst_i or posedge clk_i) begin
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always @(posedge rst_i or posedge clk_i) begin
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if (rst_i)
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if (rst_i)
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ack_internal <= 1'b0;
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ack_internal <= 1'b0;
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else if (ack_internal)
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else if (ack_internal)
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ack_internal <= 1'b0;
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ack_internal <= 1'b0;
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else if (stb_i)
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else if (stb_i)
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ack_internal <= 1'b1;
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ack_internal <= 1'b1;
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else
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else
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ack_internal <= ack_internal;
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ack_internal <= ack_internal;
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end
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end
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assign ack_o = ack_internal;
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assign ack_o = ack_internal;
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assign dat_o[31:0] = data_in[31:0];
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assign dat_o[31:0] = data_in[31:0];
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endmodule
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endmodule
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