`timescale 1ns/1ns
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`timescale 1ns/1ns
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module ha1588_axi
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module ha1588_axi
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#(
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#(
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parameter integer C_S_AXI_REG_ADDR_WIDTH = 32,
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parameter integer C_S_AXI_REG_ADDR_WIDTH = 32,
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parameter integer C_S_AXI_REG_DATA_WIDTH = 32,
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parameter integer C_S_AXI_REG_DATA_WIDTH = 32,
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parameter integer C_EXTERNAL_INTR_OUT_WIDTH = 1
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parameter integer C_EXTERNAL_INTR_OUT_WIDTH = 1
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)
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)
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(
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(
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// Register Slave System Signals
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// Register Slave System Signals
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input wire S_AXI_REG_ACLK,
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input wire S_AXI_REG_ACLK,
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input wire S_AXI_REG_ARESETN,
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input wire S_AXI_REG_ARESETN,
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// Register Slave Interface Write Address Ports
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// Register Slave Interface Write Address Ports
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input wire [C_S_AXI_REG_ADDR_WIDTH-1:0] S_AXI_REG_AWADDR,
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input wire [C_S_AXI_REG_ADDR_WIDTH-1:0] S_AXI_REG_AWADDR,
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input wire [3-1:0] S_AXI_REG_AWPROT,
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input wire [3-1:0] S_AXI_REG_AWPROT,
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input wire S_AXI_REG_AWVALID,
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input wire S_AXI_REG_AWVALID,
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output wire S_AXI_REG_AWREADY,
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output wire S_AXI_REG_AWREADY,
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// Register Slave Interface Write Data Ports
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// Register Slave Interface Write Data Ports
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input wire [C_S_AXI_REG_DATA_WIDTH-1:0] S_AXI_REG_WDATA,
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input wire [C_S_AXI_REG_DATA_WIDTH-1:0] S_AXI_REG_WDATA,
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input wire [C_S_AXI_REG_DATA_WIDTH/8-1:0] S_AXI_REG_WSTRB,
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input wire [C_S_AXI_REG_DATA_WIDTH/8-1:0] S_AXI_REG_WSTRB,
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input wire S_AXI_REG_WVALID,
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input wire S_AXI_REG_WVALID,
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output wire S_AXI_REG_WREADY,
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output wire S_AXI_REG_WREADY,
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// Register Slave Interface Write Response Ports
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// Register Slave Interface Write Response Ports
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output wire [2-1:0] S_AXI_REG_BRESP,
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output wire [2-1:0] S_AXI_REG_BRESP,
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output wire S_AXI_REG_BVALID,
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output reg S_AXI_REG_BVALID,
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input wire S_AXI_REG_BREADY,
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input wire S_AXI_REG_BREADY,
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// Register Slave Interface Read Address Ports
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// Register Slave Interface Read Address Ports
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input wire [C_S_AXI_REG_ADDR_WIDTH-1:0] S_AXI_REG_ARADDR,
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input wire [C_S_AXI_REG_ADDR_WIDTH-1:0] S_AXI_REG_ARADDR,
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input wire [3-1:0] S_AXI_REG_ARPROT,
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input wire [3-1:0] S_AXI_REG_ARPROT,
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input wire S_AXI_REG_ARVALID,
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input wire S_AXI_REG_ARVALID,
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output wire S_AXI_REG_ARREADY,
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output wire S_AXI_REG_ARREADY,
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// Register Slave Interface Read Data Ports
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// Register Slave Interface Read Data Ports
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output wire [C_S_AXI_REG_DATA_WIDTH-1:0] S_AXI_REG_RDATA,
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output wire [C_S_AXI_REG_DATA_WIDTH-1:0] S_AXI_REG_RDATA,
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output wire [2-1:0] S_AXI_REG_RRESP,
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output wire [2-1:0] S_AXI_REG_RRESP,
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output reg S_AXI_REG_RVALID,
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output reg S_AXI_REG_RVALID,
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input wire S_AXI_REG_RREADY,
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input wire S_AXI_REG_RREADY,
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// Interrupt Output Ports
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// Interrupt Output Ports
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output wire INTR_OUT,
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output wire INTR_OUT,
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// RTC and TSU Ports
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// RTC and TSU Ports
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input wire rtc_clk,
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input wire rtc_clk,
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output wire [31:0] rtc_time_ptp_ns,
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output wire [31:0] rtc_time_ptp_ns,
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output wire [47:0] rtc_time_ptp_sec,
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output wire [47:0] rtc_time_ptp_sec,
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output wire rtc_time_one_pps,
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output wire rtc_time_one_pps,
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input wire rx_gmii_clk,
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input wire rx_gmii_clk,
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input wire rx_gmii_ctrl,
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input wire rx_gmii_ctrl,
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input wire [ 7:0] rx_gmii_data,
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input wire [ 7:0] rx_gmii_data,
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input wire rx_giga_mode,
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input wire rx_giga_mode,
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input wire tx_gmii_clk,
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input wire tx_gmii_clk,
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input wire tx_gmii_ctrl,
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input wire tx_gmii_ctrl,
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input wire [ 7:0] tx_gmii_data,
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input wire [ 7:0] tx_gmii_data,
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input wire tx_giga_mode
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input wire tx_giga_mode
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);
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);
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wire up_wr;
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wire up_wr;
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wire up_rd;
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wire up_rd;
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wire [ 7:0] up_addr;
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wire [ 7:0] up_addr;
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wire [31:0] up_data_wr;
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wire [31:0] up_data_wr;
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wire [31:0] up_data_rd;
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wire [31:0] up_data_rd;
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// AXI interface
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// AXI interface
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//
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//
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// TODO: to support interleaved write address channel and write data channel,
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// TODO: to support interleaved write address channel and write data channel,
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// with FIFO for each channel.
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// with FIFO for each channel.
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// TODO: to support write data byte select
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// TODO: to support write data byte select
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// TODO: to support write response channel holding
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// TODO: to support write response channel holding
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// TODO: to support read response channel holding
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// TODO: to support read response channel holding
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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assign S_AXI_REG_AWREADY = 1'b1;
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assign S_AXI_REG_AWREADY = 1'b1;
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assign S_AXI_REG_WREADY = 1'b1;
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assign S_AXI_REG_WREADY = 1'b1;
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assign S_AXI_REG_BRESP = 2'b00;
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assign S_AXI_REG_BRESP = 2'b00;
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assign S_AXI_REG_BVALID = S_AXI_REG_WVALID;
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always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
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if (!S_AXI_REG_ARESETN) S_AXI_REG_BVALID <= 1'b0;
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else S_AXI_REG_BVALID <= S_AXI_REG_WVALID;
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end
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assign S_AXI_REG_ARREADY = 1'b1;
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assign S_AXI_REG_ARREADY = 1'b1;
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assign S_AXI_REG_RDATA = up_data_rd;
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assign S_AXI_REG_RDATA = up_data_rd;
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assign S_AXI_REG_RRESP = 2'b00;
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assign S_AXI_REG_RRESP = 2'b00;
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always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
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always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
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if (!S_AXI_REG_ARESETN) S_AXI_REG_RVALID <= 1'b0;
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if (!S_AXI_REG_ARESETN) S_AXI_REG_RVALID <= 1'b0;
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else S_AXI_REG_RVALID <= S_AXI_REG_ARVALID;
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else S_AXI_REG_RVALID <= S_AXI_REG_ARVALID;
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end
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end
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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// Interrupt interface
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// Interrupt interface
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//
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//
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// TODO: to support interrupt generation
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// TODO: to support interrupt generation
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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assign INTR_OUT = 1'b0;
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assign INTR_OUT = 1'b0;
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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// Local Bus interface
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// Local Bus interface
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//
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//
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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assign up_wr = S_AXI_REG_WVALID;
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assign up_wr = S_AXI_REG_WVALID;
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assign up_rd = S_AXI_REG_ARVALID;
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assign up_rd = S_AXI_REG_ARVALID;
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assign up_addr = S_AXI_REG_AWVALID? S_AXI_REG_AWADDR : S_AXI_REG_ARADDR;
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assign up_addr = S_AXI_REG_AWVALID? S_AXI_REG_AWADDR : S_AXI_REG_ARADDR;
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assign up_data_wr = S_AXI_REG_WDATA;
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assign up_data_wr = S_AXI_REG_WDATA;
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ha1588 ha1588_inst (
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ha1588 ha1588_inst (
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.rst(!S_AXI_REG_ARESETN),
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.rst(!S_AXI_REG_ARESETN),
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.clk(S_AXI_REG_ACLK),
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.clk(S_AXI_REG_ACLK),
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.wr_in(up_wr),
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.wr_in(up_wr),
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.rd_in(up_rd),
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.rd_in(up_rd),
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.addr_in(up_addr),
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.addr_in(up_addr),
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.data_in(up_data_wr),
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.data_in(up_data_wr),
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.data_out(up_data_rd),
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.data_out(up_data_rd),
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.rtc_clk(rtc_clk),
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.rtc_clk(rtc_clk),
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.rtc_time_ptp_ns(rtc_time_ptp_ns),
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.rtc_time_ptp_ns(rtc_time_ptp_ns),
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.rtc_time_ptp_sec(rtc_time_ptp_sec),
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.rtc_time_ptp_sec(rtc_time_ptp_sec),
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.rtc_time_one_pps(rtc_time_one_pps),
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.rtc_time_one_pps(rtc_time_one_pps),
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.rx_gmii_clk(rx_gmii_clk),
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.rx_gmii_clk(rx_gmii_clk),
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.rx_gmii_ctrl(rx_gmii_ctrl),
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.rx_gmii_ctrl(rx_gmii_ctrl),
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.rx_gmii_data(rx_gmii_data),
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.rx_gmii_data(rx_gmii_data),
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.rx_giga_mode(giga_mode),
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.rx_giga_mode(giga_mode),
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.tx_gmii_clk(tx_gmii_clk),
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.tx_gmii_clk(tx_gmii_clk),
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.tx_gmii_ctrl(tx_gmii_ctrl),
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.tx_gmii_ctrl(tx_gmii_ctrl),
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.tx_gmii_data(tx_gmii_data),
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.tx_gmii_data(tx_gmii_data),
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.tx_giga_mode(giga_mode)
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.tx_giga_mode(giga_mode)
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);
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);
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endmodule
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endmodule
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