/*
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/*
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* $ptp_drv_bfm.c
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* $ptp_drv_bfm.c
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*
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*
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* Copyright (c) 2012, BBY&HW. All rights reserved.
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* Copyright (c) 2012, BABY&HW. All rights reserved.
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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* version 2.1 of the License, or (at your option) any later version.
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*
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*
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* This library is distributed in the hope that it will be useful,
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* Lesser General Public License for more details.
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*
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*
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* You should have received a copy of the GNU Lesser General Public
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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* MA 02110-1301 USA
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include "svdpi.h"
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#include "svdpi.h"
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#include "../dpiheader.h"
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#include "../dpiheader.h"
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// define RTC address values
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// define RTC address values
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#define RTC_CTRL 0x00000000
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#define RTC_CTRL 0x00000000
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#define RTC_NULL_0x4 0x00000004
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#define RTC_NULL_0x4 0x00000004
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#define RTC_NULL_0x8 0x00000008
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#define RTC_NULL_0x8 0x00000008
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#define RTC_NULL_0xC 0x0000000C
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#define RTC_NULL_0xC 0x0000000C
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#define RTC_TIME_SEC_H_LOAD 0x00000010
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#define RTC_TIME_SEC_H_LOAD 0x00000010
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#define RTC_TIME_SEC_L_LOAD 0x00000014
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#define RTC_TIME_SEC_L_LOAD 0x00000014
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#define RTC_TIME_NSC_H_LOAD 0x00000018
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#define RTC_TIME_NSC_H_LOAD 0x00000018
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#define RTC_TIME_NSC_L_LOAD 0x0000001C
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#define RTC_TIME_NSC_L_LOAD 0x0000001C
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#define RTC_PERIOD_H_LOAD 0x00000020
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#define RTC_PERIOD_H_LOAD 0x00000020
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#define RTC_PERIOD_L_LOAD 0x00000024
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#define RTC_PERIOD_L_LOAD 0x00000024
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#define RTC_ACCMOD_H_LOAD 0x00000028
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#define RTC_ACCMOD_H_LOAD 0x00000028
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#define RTC_ACCMOD_L_LOAD 0x0000002C
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#define RTC_ACCMOD_L_LOAD 0x0000002C
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#define RTC_ADJNUM_LOAD 0x00000030
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#define RTC_ADJNUM_LOAD 0x00000030
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#define RTC_NULL_0x34 0x00000034
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#define RTC_NULL_0x34 0x00000034
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#define RTC_ADJPER_H_LOAD 0x00000038
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#define RTC_ADJPER_H_LOAD 0x00000038
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#define RTC_ADJPER_L_LOAD 0x0000003C
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#define RTC_ADJPER_L_LOAD 0x0000003C
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#define RTC_TIME_SEC_H_READ 0x00000040
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#define RTC_TIME_SEC_H_READ 0x00000040
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#define RTC_TIME_SEC_L_READ 0x00000044
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#define RTC_TIME_SEC_L_READ 0x00000044
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#define RTC_TIME_NSC_H_READ 0x00000048
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#define RTC_TIME_NSC_H_READ 0x00000048
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#define RTC_TIME_NSC_L_READ 0x0000004C
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#define RTC_TIME_NSC_L_READ 0x0000004C
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// define RTC data values
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// define RTC data values
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#define RTC_SET_CTRL_0 0x0
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#define RTC_SET_CTRL_0 0x0
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#define RTC_GET_TIME 0x1
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#define RTC_GET_TIME 0x1
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#define RTC_SET_ADJ 0x2
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#define RTC_SET_ADJ 0x2
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#define RTC_SET_PERIOD 0x4
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#define RTC_SET_PERIOD 0x4
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#define RTC_SET_TIME 0x8
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#define RTC_SET_TIME 0x8
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#define RTC_SET_RESET 0x10
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#define RTC_SET_RESET 0x10
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#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
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#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
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#define RTC_ACCMOD_L 0x0 // 256 for 8bit
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#define RTC_ACCMOD_L 0x0 // 256 for 8bit
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#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
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#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
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#define RTC_PERIOD_L 0x0
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#define RTC_PERIOD_L 0x0
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// define TSU address values
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// define TSU address values
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#define TSU_CTRL 0x00000050
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#define TSU_CTRL 0x00000050
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#define TSU_RXQUE_STATUS 0x00000054
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#define TSU_RXQUE_STATUS 0x00000054
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#define TSU_TXQUE_STATUS 0x00000058
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#define TSU_TXQUE_STATUS 0x00000058
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#define TSU_NULL_0x5C 0x0000005C
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#define TSU_NULL_0x5C 0x0000005C
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#define TSU_RXQUE_DATA_H 0x00000060
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#define TSU_RXQUE_DATA_HH 0x00000060
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#define TSU_RXQUE_DATA_L 0x00000064
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#define TSU_RXQUE_DATA_HL 0x00000064
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#define TSU_TXQUE_DATA_H 0x00000068
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#define TSU_RXQUE_DATA_LH 0x00000068
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#define TSU_TXQUE_DATA_L 0x0000006C
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#define TSU_RXQUE_DATA_LL 0x0000006C
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#define TSU_TXQUE_DATA_HH 0x00000070
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#define TSU_TXQUE_DATA_HL 0x00000074
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#define TSU_TXQUE_DATA_LH 0x00000078
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#define TSU_TXQUE_DATA_LL 0x0000007C
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// define TSU data values
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// define TSU data values
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#define TSU_SET_CTRL_0 0x0
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#define TSU_SET_CTRL_0 0x0
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#define TSU_GET_TXQUE 0x1
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#define TSU_GET_TXQUE 0x1
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#define TSU_GET_RXQUE 0x4
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#define TSU_GET_RXQUE 0x4
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#define TSU_SET_RESET 0xA
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#define TSU_SET_RXRST 0x8
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#define TSU_SET_TXRST 0x2
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int ptp_drv_bfm_c(double fw_delay)
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int ptp_drv_bfm_c(double fw_delay)
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{
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{
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unsigned int cpu_addr_i;
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unsigned int cpu_addr_i;
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unsigned int cpu_data_i;
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unsigned int cpu_data_i;
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unsigned int cpu_data_o;
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unsigned int cpu_data_o;
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// LOAD RTC PERIOD AND ACC_MODULO
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// LOAD RTC PERIOD AND ACC_MODULO
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cpu_addr_i = RTC_PERIOD_H_LOAD;
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cpu_addr_i = RTC_PERIOD_H_LOAD;
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cpu_data_i = RTC_PERIOD_H;
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cpu_data_i = RTC_PERIOD_H;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_PERIOD_L_LOAD;
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cpu_addr_i = RTC_PERIOD_L_LOAD;
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cpu_data_i = RTC_PERIOD_L;
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cpu_data_i = RTC_PERIOD_L;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_ACCMOD_H_LOAD;
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cpu_addr_i = RTC_ACCMOD_H_LOAD;
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cpu_data_i = RTC_ACCMOD_H;
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cpu_data_i = RTC_ACCMOD_H;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_ACCMOD_L_LOAD;
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cpu_addr_i = RTC_ACCMOD_L_LOAD;
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cpu_data_i = RTC_ACCMOD_L;
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cpu_data_i = RTC_ACCMOD_L;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_PERIOD;
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cpu_data_i = RTC_SET_PERIOD;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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// RESET RTC AND TSU
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// RESET RTC
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_RESET;
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cpu_data_i = RTC_SET_RESET;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_CTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_CTRL;
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cpu_data_i = TSU_SET_RESET;
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cpu_wr(cpu_addr_i, cpu_data_i);
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// READ RTC SEC AND NS
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// READ RTC SEC AND NS
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_GET_TIME;
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cpu_data_i = RTC_GET_TIME;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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do {
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do {
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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//printf("%08x\n", (cpu_data_o & 0x1));
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//printf("%08x\n", (cpu_data_o & 0x1));
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} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
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} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
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cpu_addr_i = RTC_TIME_SEC_H_READ;
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cpu_addr_i = RTC_TIME_SEC_H_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("\ntime: \n%08x\n", cpu_data_o);
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printf("\ntime: \n%08x\n", cpu_data_o);
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cpu_addr_i = RTC_TIME_SEC_L_READ;
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cpu_addr_i = RTC_TIME_SEC_L_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("%08x\n", cpu_data_o);
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printf("%08x\n", cpu_data_o);
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cpu_addr_i = RTC_TIME_NSC_H_READ;
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cpu_addr_i = RTC_TIME_NSC_H_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("%08x\n", cpu_data_o);
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printf("%08x\n", cpu_data_o);
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cpu_addr_i = RTC_TIME_NSC_L_READ;
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cpu_addr_i = RTC_TIME_NSC_L_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("%08x\n", cpu_data_o);
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printf("%08x\n", cpu_data_o);
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// LOAD RTC SEC AND NS
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// LOAD RTC SEC AND NS
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cpu_addr_i = RTC_TIME_SEC_H_LOAD;
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cpu_addr_i = RTC_TIME_SEC_H_LOAD;
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cpu_data_i = 0x0;
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cpu_data_i = 0x0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_TIME_SEC_L_LOAD;
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cpu_addr_i = RTC_TIME_SEC_L_LOAD;
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cpu_data_i = 0x1;
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cpu_data_i = 0x1;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_TIME_NSC_H_LOAD;
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cpu_addr_i = RTC_TIME_NSC_H_LOAD;
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cpu_data_i = RTC_ACCMOD_H - 0xA;
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cpu_data_i = RTC_ACCMOD_H - 0xA;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_TIME_NSC_L_LOAD;
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cpu_addr_i = RTC_TIME_NSC_L_LOAD;
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cpu_data_i = 0x0;
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cpu_data_i = 0x0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_TIME;
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cpu_data_i = RTC_SET_TIME;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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// LOAD RTC ADJ
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// LOAD RTC ADJ
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cpu_addr_i = RTC_ADJNUM_LOAD;
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cpu_addr_i = RTC_ADJNUM_LOAD;
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cpu_data_i = 0x100;
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cpu_data_i = 0x100;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_ADJPER_H_LOAD;
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cpu_addr_i = RTC_ADJPER_H_LOAD;
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cpu_data_i = 0x1;
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cpu_data_i = 0x1;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_ADJPER_L_LOAD;
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cpu_addr_i = RTC_ADJPER_L_LOAD;
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cpu_data_i = 0x20;
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cpu_data_i = 0x20;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_ADJ;
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cpu_data_i = RTC_SET_ADJ;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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// READ RTC SEC AND NS
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// READ RTC SEC AND NS
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_data_i = RTC_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_data_i = RTC_GET_TIME;
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cpu_data_i = RTC_GET_TIME;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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do {
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do {
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cpu_addr_i = RTC_CTRL;
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cpu_addr_i = RTC_CTRL;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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//printf("%08x\n", (cpu_data_o & 0x1));
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//printf("%08x\n", (cpu_data_o & 0x1));
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} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
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} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
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cpu_addr_i = RTC_TIME_SEC_H_READ;
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cpu_addr_i = RTC_TIME_SEC_H_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("\ntime: \n%08x\n", cpu_data_o);
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printf("\ntime: \n%08x\n", cpu_data_o);
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cpu_addr_i = RTC_TIME_SEC_L_READ;
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cpu_addr_i = RTC_TIME_SEC_L_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("%08x\n", cpu_data_o);
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printf("%08x\n", cpu_data_o);
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cpu_addr_i = RTC_TIME_NSC_H_READ;
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cpu_addr_i = RTC_TIME_NSC_H_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("%08x\n", cpu_data_o);
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printf("%08x\n", cpu_data_o);
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cpu_addr_i = RTC_TIME_NSC_L_READ;
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cpu_addr_i = RTC_TIME_NSC_L_READ;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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printf("%08x\n", cpu_data_o);
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printf("%08x\n", cpu_data_o);
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int i;
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int i;
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int rx_queue_num;
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int rx_queue_num;
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int tx_queue_num;
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int tx_queue_num;
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// RESET TSU
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cpu_addr_i = TSU_CTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_CTRL;
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cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;
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cpu_wr(cpu_addr_i, cpu_data_i);
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// READ TSU
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while (1) {
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while (1) {
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|
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// POLL TSU RX STATUS
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// POLL TSU RX STATUS
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cpu_addr_i = TSU_RXQUE_STATUS;
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cpu_addr_i = TSU_RXQUE_STATUS;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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rx_queue_num = cpu_data_o;
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rx_queue_num = cpu_data_o;
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//printf("%08x\n", rx_queue_num);
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//printf("%08x\n", rx_queue_num);
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|
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if (rx_queue_num > 0x0) {
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if (rx_queue_num > 0x0) {
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// READ TSU RX FIFO
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for (i=rx_queue_num; i>0; i--) {
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for (i=rx_queue_num; i>0; i--) {
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// READ TSU RX FIFO
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_CTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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|
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_CTRL;
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cpu_data_i = TSU_GET_RXQUE;
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cpu_data_i = TSU_GET_RXQUE;
|
cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
do {
|
do {
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_CTRL;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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//printf("%08x\n", (cpu_data_o & 0x1));
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//printf("%08x\n", (cpu_data_o & 0x1));
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} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
|
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
|
cpu_addr_i = TSU_RXQUE_DATA_H;
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|
|
cpu_addr_i = TSU_RXQUE_DATA_HH;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
printf("\nRx stamp: \n%08x\n", cpu_data_o);
|
printf("\nRx stamp: \n%08x\n", cpu_data_o);
|
cpu_addr_i = TSU_RXQUE_DATA_L;
|
|
|
cpu_addr_i = TSU_RXQUE_DATA_HL;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = TSU_RXQUE_DATA_LH;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = TSU_RXQUE_DATA_LL;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
// READ RTC SEC AND NS
|
|
cpu_addr_i = RTC_CTRL;
|
|
cpu_data_i = RTC_SET_CTRL_0;
|
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
|
cpu_addr_i = RTC_CTRL;
|
|
cpu_data_i = RTC_GET_TIME;
|
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
|
do {
|
|
cpu_addr_i = RTC_CTRL;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
//printf("%08x\n", (cpu_data_o & 0x1));
|
|
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
|
|
|
|
cpu_addr_i = RTC_TIME_SEC_H_READ;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("\ntime: \n%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = RTC_TIME_SEC_L_READ;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = RTC_TIME_NSC_H_READ;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = RTC_TIME_NSC_L_READ;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
printf("%08x\n", cpu_data_o);
|
printf("%08x\n", cpu_data_o);
|
}
|
}
|
}
|
}
|
|
|
// POLL TSU TX STATUS
|
// POLL TSU TX STATUS
|
cpu_addr_i = TSU_TXQUE_STATUS;
|
cpu_addr_i = TSU_TXQUE_STATUS;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
tx_queue_num = cpu_data_o;
|
tx_queue_num = cpu_data_o;
|
//printf("%08x\n", tx_queue_num);
|
//printf("%08x\n", tx_queue_num);
|
|
|
if (tx_queue_num > 0x0) {
|
if (tx_queue_num > 0x0) {
|
// READ TSU TX FIFO
|
|
for (i=tx_queue_num; i>0; i--) {
|
for (i=tx_queue_num; i>0; i--) {
|
|
|
|
// READ TSU TX FIFO
|
cpu_addr_i = TSU_CTRL;
|
cpu_addr_i = TSU_CTRL;
|
cpu_data_i = TSU_SET_CTRL_0;
|
cpu_data_i = TSU_SET_CTRL_0;
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
cpu_addr_i = TSU_CTRL;
|
cpu_addr_i = TSU_CTRL;
|
cpu_data_i = TSU_GET_TXQUE;
|
cpu_data_i = TSU_GET_TXQUE;
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
do {
|
do {
|
cpu_addr_i = TSU_CTRL;
|
cpu_addr_i = TSU_CTRL;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
//printf("%08x\n", (cpu_data_o & 0x1));
|
//printf("%08x\n", (cpu_data_o & 0x1));
|
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
|
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
|
cpu_addr_i = TSU_TXQUE_DATA_H;
|
|
|
cpu_addr_i = TSU_TXQUE_DATA_HH;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
printf("\nTx stamp: \n%08x\n", cpu_data_o);
|
printf("\nTx stamp: \n%08x\n", cpu_data_o);
|
cpu_addr_i = TSU_TXQUE_DATA_L;
|
|
|
cpu_addr_i = TSU_TXQUE_DATA_HL;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = TSU_TXQUE_DATA_LH;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = TSU_TXQUE_DATA_LL;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
// READ RTC SEC AND NS
|
|
cpu_addr_i = RTC_CTRL;
|
|
cpu_data_i = RTC_SET_CTRL_0;
|
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
|
cpu_addr_i = RTC_CTRL;
|
|
cpu_data_i = RTC_GET_TIME;
|
|
cpu_wr(cpu_addr_i, cpu_data_i);
|
|
|
|
do {
|
|
cpu_addr_i = RTC_CTRL;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
//printf("%08x\n", (cpu_data_o & 0x1));
|
|
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
|
|
|
|
cpu_addr_i = RTC_TIME_SEC_H_READ;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("\ntime: \n%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = RTC_TIME_SEC_L_READ;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = RTC_TIME_NSC_H_READ;
|
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
|
printf("%08x\n", cpu_data_o);
|
|
|
|
cpu_addr_i = RTC_TIME_NSC_L_READ;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
printf("%08x\n", cpu_data_o);
|
printf("%08x\n", cpu_data_o);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
// READ BACK ALL REGISTERS
|
// READ BACK ALL REGISTERS
|
for (;;)
|
for (;;)
|
{
|
{
|
int t;
|
int t;
|
for (t=0; t<=0x5c; t=t+4)
|
for (t=0; t<=0xff; t=t+4)
|
{
|
{
|
cpu_hd(10);
|
cpu_hd(10);
|
|
|
cpu_addr_i = t;
|
cpu_addr_i = t;
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
cpu_rd(cpu_addr_i, &cpu_data_o);
|
}
|
}
|
}
|
}
|
|
|
return(0); /* Return success (required by tasks) */
|
return(0); /* Return success (required by tasks) */
|
}
|
}
|
|
|