-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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-- File: PCK_CRC16_D8.vhd
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-- File: PCK_CRC16_D8.vhd
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-- Date: Wed Feb 7 08:06:05 2001
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-- Date: Wed Feb 7 08:06:05 2001
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--
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--
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-- Copyright (C) 1999 Easics NV.
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-- Copyright (C) 1999 Easics NV.
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-- This source file may be used and distributed without restriction
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-- This source file may be used and distributed without restriction
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-- provided that this copyright statement is not removed from the file
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-- provided that this copyright statement is not removed from the file
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-- and that any derivative work contains the original copyright notice
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-- and that any derivative work contains the original copyright notice
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-- and the associated disclaimer.
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-- and the associated disclaimer.
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--
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--
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-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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--
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--
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-- Purpose: VHDL package containing a synthesizable CRC function
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-- Purpose: VHDL package containing a synthesizable CRC function
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-- * polynomial: (0 5 12 16)
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-- * polynomial: (0 5 12 16)
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-- * data width: 8
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-- * data width: 8
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--
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--
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-- Info: jand@easics.be (Jan Decaluwe)
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-- Info: jand@easics.be (Jan Decaluwe)
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-- http://www.easics.com
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-- http://www.easics.com
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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package PCK_CRC16_D8 is
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package PCK_CRC16_D8 is
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-- polynomial: (0 5 12 16)
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-- polynomial: (0 5 12 16)
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-- data width: 8
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-- data width: 8
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-- convention: the first serial data bit is D(7)
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-- convention: the first serial data bit is D(7)
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function nextCRC16_D8
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function nextCRC16_D8
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( Data: std_logic_vector(7 downto 0);
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( Data: std_logic_vector(7 downto 0);
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CRC: std_logic_vector(15 downto 0) )
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CRC: std_logic_vector(15 downto 0) )
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return std_logic_vector;
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return std_logic_vector;
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end PCK_CRC16_D8;
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end PCK_CRC16_D8;
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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package body PCK_CRC16_D8 is
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package body PCK_CRC16_D8 is
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-- polynomial: (0 5 12 16)
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-- polynomial: (0 5 12 16)
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-- data width: 8
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-- data width: 8
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-- convention: the first serial data bit is D(7)
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-- convention: the first serial data bit is D(7)
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function nextCRC16_D8
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function nextCRC16_D8
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( Data: std_logic_vector(7 downto 0);
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( Data: std_logic_vector(7 downto 0);
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CRC: std_logic_vector(15 downto 0) )
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CRC: std_logic_vector(15 downto 0) )
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return std_logic_vector is
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return std_logic_vector is
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variable D: std_logic_vector(7 downto 0);
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variable D: std_logic_vector(7 downto 0);
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variable C: std_logic_vector(15 downto 0);
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variable C: std_logic_vector(15 downto 0);
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variable NewCRC: std_logic_vector(15 downto 0);
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variable NewCRC: std_logic_vector(15 downto 0);
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begin
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begin
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D := Data;
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D := Data;
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C := CRC;
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C := CRC;
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NewCRC(0) := D(4) xor D(0) xor C(8) xor C(12);
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NewCRC(0) := D(4) xor D(0) xor C(8) xor C(12);
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NewCRC(1) := D(5) xor D(1) xor C(9) xor C(13);
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NewCRC(1) := D(5) xor D(1) xor C(9) xor C(13);
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NewCRC(2) := D(6) xor D(2) xor C(10) xor C(14);
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NewCRC(2) := D(6) xor D(2) xor C(10) xor C(14);
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NewCRC(3) := D(7) xor D(3) xor C(11) xor C(15);
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NewCRC(3) := D(7) xor D(3) xor C(11) xor C(15);
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NewCRC(4) := D(4) xor C(12);
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NewCRC(4) := D(4) xor C(12);
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NewCRC(5) := D(5) xor D(4) xor D(0) xor C(8) xor C(12) xor C(13);
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NewCRC(5) := D(5) xor D(4) xor D(0) xor C(8) xor C(12) xor C(13);
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NewCRC(6) := D(6) xor D(5) xor D(1) xor C(9) xor C(13) xor C(14);
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NewCRC(6) := D(6) xor D(5) xor D(1) xor C(9) xor C(13) xor C(14);
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NewCRC(7) := D(7) xor D(6) xor D(2) xor C(10) xor C(14) xor C(15);
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NewCRC(7) := D(7) xor D(6) xor D(2) xor C(10) xor C(14) xor C(15);
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NewCRC(8) := D(7) xor D(3) xor C(0) xor C(11) xor C(15);
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NewCRC(8) := D(7) xor D(3) xor C(0) xor C(11) xor C(15);
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NewCRC(9) := D(4) xor C(1) xor C(12);
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NewCRC(9) := D(4) xor C(1) xor C(12);
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NewCRC(10) := D(5) xor C(2) xor C(13);
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NewCRC(10) := D(5) xor C(2) xor C(13);
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NewCRC(11) := D(6) xor C(3) xor C(14);
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NewCRC(11) := D(6) xor C(3) xor C(14);
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NewCRC(12) := D(7) xor D(4) xor D(0) xor C(4) xor C(8) xor C(12) xor
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NewCRC(12) := D(7) xor D(4) xor D(0) xor C(4) xor C(8) xor C(12) xor
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C(15);
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C(15);
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NewCRC(13) := D(5) xor D(1) xor C(5) xor C(9) xor C(13);
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NewCRC(13) := D(5) xor D(1) xor C(5) xor C(9) xor C(13);
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NewCRC(14) := D(6) xor D(2) xor C(6) xor C(10) xor C(14);
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NewCRC(14) := D(6) xor D(2) xor C(6) xor C(10) xor C(14);
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NewCRC(15) := D(7) xor D(3) xor C(7) xor C(11) xor C(15);
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NewCRC(15) := D(7) xor D(3) xor C(7) xor C(11) xor C(15);
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return NewCRC;
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return NewCRC;
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end nextCRC16_D8;
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end nextCRC16_D8;
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end PCK_CRC16_D8;
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end PCK_CRC16_D8;
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