-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Title : HDLC components package
|
-- Title : HDLC components package
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-- Project : HDLC controller
|
-- Project : HDLC controller
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : hdlc_components_pkg.vhd
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-- File : hdlc_components_pkg.vhd
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Organization: OpenIPCore Project
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-- Created : 2000/12/30
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-- Created : 2000/12/30
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-- Last update: 2001/01/26
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-- Last update: 2001/04/27
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-- Platform :
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-- Platform :
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Synthesizers:
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-- Synthesizers:
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-- Target :
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-- Target :
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-- Dependency : ieee.std_logic_1164
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-- Dependency : ieee.std_logic_1164
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description: HDLC components package
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-- Description: HDLC components package
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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-- Copyright (c) 2000 Jamil Khatib
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--
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
|
-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-- http://www.opencores.org/OIPC/license.shtml
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Revision Number : 1
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-- Revision Number : 1
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-- Version : 0.1
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-- Version : 0.1
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-- Date : 30 Dec 2000
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-- Date : 30 Dec 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Created
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-- Desccription : Created
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-- ToOptimize :
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-- ToOptimize :
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-- Bugs :
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-- Bugs :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Revision Number : 2
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-- Revision Number : 2
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-- Version : 0.2
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-- Version : 0.2
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-- Date : 12 Jan 2001
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-- Date : 12 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : RxEnable bug fixed
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-- Desccription : RxEnable bug fixed
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Revision Number : 3
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-- Revision Number : 3
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-- Version : 0.3
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-- Version : 0.3
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-- Date : 16 Jan 2001
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-- Date : 16 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : TX componentes added
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-- Desccription : TX componentes added
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision Number : 4
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-- Version : 0.4
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-- Date : 22 March 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Tx Top components added
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--
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|
-------------------------------------------------------------------------------
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-- Revision Number : 5
|
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-- Version : 0.5
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-- Date : 9 April 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Rx Top components added
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--
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|
-------------------------------------------------------------------------------
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|
-- $Log: not supported by cvs2svn $
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|
-- Revision 1.11 2001/04/27 18:21:59 jamil
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|
-- After Prelimenray simulation
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--
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-- Revision 1.10 2001/04/22 20:08:16 jamil
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-- Top level simulation
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--
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-- Revision 1.7 2001/04/14 15:23:34 jamil
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-- Rx Components added
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--
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-- Revision 1.6 2001/03/22 21:58:46 jamil
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-- Top Tx Components added
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--
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|
-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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package hdlc_components_pkg is
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package hdlc_components_pkg is
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component hdlc_ent
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generic (
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FCS_TYPE : integer;
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ADD_WIDTH : integer);
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port (
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Txclk : in std_logic;
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RxClk : in std_logic;
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Tx : out std_logic;
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Rx : in std_logic;
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TxEN : in std_logic;
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RxEn : in std_logic;
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RST_I : in std_logic;
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CLK_I : in std_logic;
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ADR_I : in std_logic_vector(2 downto 0);
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DAT_O : out std_logic_vector(31 downto 0);
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DAT_I : in std_logic_vector(31 downto 0);
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WE_I : in std_logic;
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STB_I : in std_logic;
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ACK_O : out std_logic;
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CYC_I : in std_logic;
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RTY_O : out std_logic;
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TAG0_O : out std_logic;
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TAG1_O : out std_logic);
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end component;
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constant ADD_WIDTH : integer := 7; -- Internal Buffers address width
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component WB_IF_ent
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generic (
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ADD_WIDTH : integer);
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port (
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CLK_I : in std_logic;
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RST_I : in std_logic;
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ACK_O : out std_logic;
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ADR_I : in std_logic_vector(2 downto 0);
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CYC_I : in std_logic;
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DAT_I : in std_logic_vector(31 downto 0);
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DAT_O : out std_logic_vector(31 downto 0);
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RTY_O : out std_logic;
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STB_I : in std_logic;
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WE_I : in std_logic;
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TAG0_O : out std_logic;
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TAG1_O : out std_logic;
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TxEnable : out std_logic;
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TxDone : in std_logic;
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TxDataInBuff : out std_logic_vector(7 downto 0);
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Txwr : out std_logic;
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TxAborted : in std_logic;
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TxAbort : out std_logic;
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TxOverflow : in std_logic;
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TxFCSen : out std_logic;
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RxFrameSize : in std_logic_vector(ADD_WIDTH-1 downto 0);
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RxRdy : in std_logic;
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RxDataBuffOut : in std_logic_vector(7 downto 0);
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RxOverflow : in std_logic;
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RxFrameError : in std_logic;
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RxFCSErr : in std_logic;
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RxRd : out std_logic;
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RxAbort : in std_logic);
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end component;
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component txSynch_ent
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port (
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rst_n : in std_logic;
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clk_D1 : in std_logic;
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clk_D2 : in std_logic;
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rdy_D1 : in std_logic;
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rdy_D2 : out std_logic;
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ack : out std_logic;
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TXD_D1 : out std_logic_vector(7 downto 0);
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TXD_D2 : in std_logic_vector(7 downto 0);
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ValidFrame_D1 : out std_logic;
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ValidFrame_D2 : in std_logic;
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AbortedTrans_D1 : in std_logic;
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AbortedTrans_D2 : out std_logic;
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AbortFrame_D1 : out std_logic;
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AbortFrame_D2 : in std_logic;
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WriteByte_D1 : out std_logic;
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WriteByte_D2 : in std_logic);
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end component;
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|
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component Txfcs_ent
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|
generic (
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FCS_TYPE : integer);
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port (
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TxClk : in std_logic;
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rst_n : in std_logic;
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|
FCSen : in std_logic;
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ValidFrame : out std_logic;
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WriteByte : out std_logic;
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rdy : in std_logic;
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ack : in std_logic;
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TxData : out std_logic_vector(7 downto 0);
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TxDataAvail : in std_logic;
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RdBuff : out std_logic;
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TxDataBuff : in std_logic_vector(7 downto 0));
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|
end component;
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|
|
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component TxBuff_ent
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|
generic (
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ADD_WIDTH : integer);
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port (
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TxClk : in std_logic;
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rst_n : in std_logic;
|
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RdBuff : in std_logic;
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Wr : in std_logic;
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TxDataAvail : out std_logic;
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TxEnable : in std_logic;
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TxDone : out std_logic;
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TxDataOutBuff : out std_logic_vector(7 downto 0);
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|
TxDataInBuff : in std_logic_vector(7 downto 0);
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Full : out std_logic);
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|
end component;
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|
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component TxChannel_ent
|
component TxChannel_ent
|
port (
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port (
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TxClk : in std_logic;
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TxClk : in std_logic;
|
rst_n : in std_logic;
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rst_n : in std_logic;
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TXEN : in std_logic;
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TXEN : in std_logic;
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Tx : out std_logic;
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Tx : out std_logic;
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ValidFrame : in std_logic;
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ValidFrame : in std_logic;
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AbortFrame : in std_logic;
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AbortFrame : in std_logic;
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AbortedTrans : out std_logic;
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AbortedTrans : out std_logic;
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WriteByte : in std_logic;
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WriteByte : in std_logic;
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rdy : out std_logic;
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rdy : out std_logic;
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TxData : in std_logic_vector(7 downto 0));
|
TxData : in std_logic_vector(7 downto 0));
|
end component;
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end component;
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|
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component TxCont_ent
|
component TxCont_ent
|
port (
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port (
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TXclk : in std_logic;
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TXclk : in std_logic;
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rst_n : in std_logic;
|
rst_n : in std_logic;
|
TXEN : in std_logic;
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TXEN : in std_logic;
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enable : out std_logic;
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enable : out std_logic;
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BackendEnable : out std_logic;
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BackendEnable : out std_logic;
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abortedTrans : in std_logic;
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abortedTrans : in std_logic;
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inProgress : in std_logic;
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inProgress : in std_logic;
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ValidFrame : in std_logic;
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ValidFrame : in std_logic;
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Frame : out std_logic;
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Frame : out std_logic;
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AbortFrame : in std_logic;
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AbortFrame : in std_logic;
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AbortTrans : out std_logic);
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AbortTrans : out std_logic);
|
end component;
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end component;
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|
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component flag_ins_ent
|
component flag_ins_ent
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port (
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port (
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TXclk : in std_logic;
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TXclk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
|
TX : out std_logic;
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TX : out std_logic;
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TXEN : in std_logic;
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TXEN : in std_logic;
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TXD : in std_logic;
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TXD : in std_logic;
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AbortFrame : in std_logic;
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AbortFrame : in std_logic;
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Frame : in std_logic);
|
Frame : in std_logic);
|
end component;
|
end component;
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|
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component ZeroIns_ent
|
component ZeroIns_ent
|
port (
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port (
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TxClk : in std_logic;
|
TxClk : in std_logic;
|
rst_n : in std_logic;
|
rst_n : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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BackendEnable : in std_logic;
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BackendEnable : in std_logic;
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abortedTrans : out std_logic;
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abortedTrans : out std_logic;
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inProgress : out std_logic;
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inProgress : out std_logic;
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ValidFrame : in std_logic;
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ValidFrame : in std_logic;
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Writebyte : in std_logic;
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Writebyte : in std_logic;
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rdy : out std_logic;
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rdy : out std_logic;
|
TXD : out std_logic;
|
TXD : out std_logic;
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Data : in std_logic_vector(7 downto 0));
|
Data : in std_logic_vector(7 downto 0));
|
end component;
|
end component;
|
|
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component rxcont_ent
|
component rxcont_ent
|
port (
|
port (
|
RxClk : in std_logic;
|
RxClk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
RxEn : in std_logic;
|
RxEn : in std_logic;
|
AbortedFrame : out std_logic;
|
AbortedFrame : out std_logic;
|
Abort : in std_logic;
|
Abort : in std_logic;
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FlagDetect : in std_logic;
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FlagDetect : in std_logic;
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ValidFrame : out std_logic;
|
ValidFrame : out std_logic;
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FrameError : out std_logic;
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FrameError : out std_logic;
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aval : in std_logic;
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aval : in std_logic;
|
initzero : out std_logic;
|
initzero : out std_logic;
|
enable : out std_logic);
|
enable : out std_logic);
|
end component;
|
end component;
|
|
|
|
|
component ZeroDetect_ent
|
component ZeroDetect_ent
|
port (
|
port (
|
|
ValidFrame : in std_logic; --New
|
Readbyte : in std_logic;
|
Readbyte : in std_logic;
|
aval : out std_logic;
|
aval : out std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
StartOfFrame : in std_logic;
|
StartOfFrame : in std_logic;
|
rdy : out std_logic;
|
rdy : out std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
RxClk : in std_logic;
|
RxClk : in std_logic;
|
RxD : in std_logic;
|
RxD : in std_logic;
|
RxData : out std_logic_vector(7 downto 0));
|
RxData : out std_logic_vector(7 downto 0));
|
end component;
|
end component;
|
|
|
component FlagDetect_ent
|
component FlagDetect_ent
|
port (
|
port (
|
Rxclk : in std_logic;
|
Rxclk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
FlagDetect : out std_logic;
|
FlagDetect : out std_logic;
|
Abort : out std_logic;
|
Abort : out std_logic;
|
RXEN : in std_logic;
|
RXEN : in std_logic;
|
RXEN_O : out std_logic;
|
RXEN_O : out std_logic;
|
RXD : out std_logic;
|
RXD : out std_logic;
|
RX : in std_logic);
|
RX : in std_logic);
|
end component;
|
end component;
|
|
|
component RxChannel_ent
|
component RxChannel_ent
|
port (
|
port (
|
Rxclk : in std_logic;
|
Rxclk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
Rx : in std_logic;
|
Rx : in std_logic;
|
RxData : out std_logic_vector(7 downto 0);
|
RxData : out std_logic_vector(7 downto 0);
|
ValidFrame : out std_logic;
|
ValidFrame : out std_logic;
|
AbortSignal : out std_logic;
|
AbortSignal : out std_logic;
|
FrameError : out std_logic;
|
FrameError : out std_logic;
|
Readbyte : in std_logic;
|
Readbyte : in std_logic;
|
rdy : out std_logic;
|
rdy : out std_logic;
|
RxEn : in std_logic);
|
RxEn : in std_logic);
|
end component;
|
end component;
|
|
|
|
component RxSynch_ent
|
|
port (
|
|
rst_n : in std_logic;
|
|
clk_D1 : in std_logic;
|
|
clk_D2 : in std_logic;
|
|
rdy_D1 : in std_logic;
|
|
rdy_D2 : out std_logic;
|
|
RXD_D1 : in std_logic_vector(7 downto 0);
|
|
RXD_D2 : out std_logic_vector(7 downto 0);
|
|
ValidFrame_D1 : in std_logic;
|
|
ValidFrame_D2 : out std_logic;
|
|
AbortSignal_D1 : in std_logic;
|
|
AbortSignal_D2 : out std_logic;
|
|
FrameError_D1 : in std_logic;
|
|
FrameError_D2 : out std_logic;
|
|
ReadByte_D1 : out std_logic;
|
|
ReadByte_D2 : in std_logic);
|
|
end component;
|
|
|
|
component RxFCS_ent
|
|
generic (
|
|
FCS_TYPE : integer);
|
|
port (
|
|
clk : in std_logic;
|
|
rst_n : in std_logic;
|
|
RxD : in std_logic_vector(7 downto 0);
|
|
ValidFrame : in std_logic;
|
|
rdy : in std_logic;
|
|
Readbyte : out std_logic;
|
|
DataBuff : out std_logic_vector(7 downto 0);
|
|
WrBuff : out std_logic;
|
|
EOF : out std_logic;
|
|
FCSen : in std_logic;
|
|
FCSerr : out std_logic);
|
|
end component;
|
|
|
|
component RxBuff_ent
|
|
generic (
|
|
FCS_TYPE : integer;
|
|
ADD_WIDTH : integer);
|
|
port (
|
|
Clk : in std_logic;
|
|
rst_n : in std_logic;
|
|
DataBuff : in std_logic_vector(7 downto 0);
|
|
EOF : in std_logic;
|
|
WrBuff : in std_logic;
|
|
FrameSize : out std_logic_vector(ADD_WIDTH-1 downto 0);
|
|
RxRdy : out std_logic;
|
|
RxDataBuffOut : out std_logic_vector(7 downto 0);
|
|
Overflow : out std_logic;
|
|
Rd : in std_logic);
|
|
end component;
|
|
|
end hdlc_components_pkg;
|
end hdlc_components_pkg;
|
|
|
