-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Title : Memory Package
|
-- Title : Memory Package
|
-- Project : Memory Cores
|
-- Project : Memory Cores
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : mem_pkg.vhd
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-- File : mem_pkg.vhd
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-- Author : Jamil Khatib
|
-- Author : Jamil Khatib
|
-- Organization: OpenIPCore Project
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-- Organization: OpenIPCore Project
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-- Created : 2000/02/29
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-- Created : 2000/02/29
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-- Last update: 2001/03/20
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-- Last update: 2001/03/20
|
-- Platform :
|
-- Platform :
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-- Simulators : Modelsim 5.2EE / Windows98, NC-Sim/Linux
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-- Simulators : Modelsim 5.2EE / Windows98, NC-Sim/Linux
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-- Synthesizers: Leonardo / Windows98
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-- Synthesizers: Leonardo / Windows98
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-- Target : Flex10K
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-- Target : Flex10K
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-- Dependency : ieee.std_logic_1164
|
-- Dependency : ieee.std_logic_1164
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-- utility.tools_pkg
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-- utility.tools_pkg
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description: Memory Package
|
-- Description: Memory Package
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Copyright (c) 2000 Jamil Khatib
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-- Copyright (c) 2000 Jamil Khatib
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--
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
|
-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it under the terms of the Openip General Public
|
-- modify it and/or implement it under the terms of the Openip General Public
|
-- License as it is going to be published by the OpenIPCore Organization and
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-- License as it is going to be published by the OpenIPCore Organization and
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-- any coming versions of this license.
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-- any coming versions of this license.
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-- You can check the draft license at
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-- You can check the draft license at
|
-- http://www.openip.org/oc/license.html
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-- http://www.openip.org/oc/license.html
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 1
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-- Revision Number : 1
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-- Version : 0.1
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-- Version : 0.1
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-- Date : 29th Feb 2000
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-- Date : 29th Feb 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Created
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-- Desccription : Created
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 2
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-- Revision Number : 2
|
-- Version : 0.2
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-- Version : 0.2
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-- Date : 29th Mar 2000
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-- Date : 29th Mar 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Memory components are added.
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-- Desccription : Memory components are added.
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--
|
--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 3
|
-- Revision Number : 3
|
-- Version : 0.3
|
-- Version : 0.3
|
-- Date : 12 Jan 2001
|
-- Date : 12 Jan 2001
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Memory components updated
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-- Desccription : Memory components updated
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--
|
--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 4
|
-- Revision Number : 4
|
-- Version : 0.31
|
-- Version : 0.31
|
-- Date : 11 March 2001
|
-- Date : 11 March 2001
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : FIFO component added
|
-- Desccription : FIFO component added
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 5
|
-- Revision Number : 5
|
-- Version : 0.5
|
-- Version : 0.5
|
-- Date : 16 April 2001
|
-- Date : 16 April 2001
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : WISHBONE components added
|
-- Desccription : WISHBONE components added
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--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
-- Revision 1.4 2001/04/16 20:14:35 jamil
|
-- Revision 1.4 2001/04/16 20:14:35 jamil
|
-- WishBone components added
|
-- WishBone components added
|
--
|
--
|
-- Revision 1.3 2001/03/20 19:39:32 jamil
|
-- Revision 1.3 2001/03/20 19:39:32 jamil
|
-- tools pkg bug fixed
|
-- tools pkg bug fixed
|
--
|
--
|
-- Revision 1.2 2001/03/11 21:22:55 jamil
|
-- Revision 1.2 2001/03/11 21:22:55 jamil
|
-- FIFO component added
|
-- FIFO component added
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
library utility;
|
library utility;
|
use utility.tools_pkg.all;
|
use utility.tools_pkg.all;
|
|
|
package mem_pkg is
|
package mem_pkg is
|
|
|
constant ADD_WIDTH : integer := 8; -- Address width
|
constant ADD_WIDTH : integer := 8; -- Address width
|
constant WIDTH : integer := 4; -- Data width
|
constant WIDTH : integer := 4; -- Data width
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
component dpmem_ent
|
component dpmem_ent
|
generic (
|
generic (
|
USE_RESET : boolean;
|
USE_RESET : boolean;
|
USE_CS : boolean;
|
USE_CS : boolean;
|
DEFAULT_OUT : std_logic;
|
DEFAULT_OUT : std_logic;
|
CLK_DOMAIN : integer;
|
CLK_DOMAIN : integer;
|
ADD_WIDTH : integer;
|
ADD_WIDTH : integer;
|
WIDTH : integer);
|
WIDTH : integer);
|
port (
|
port (
|
W_clk : in std_logic;
|
W_clk : in std_logic;
|
R_clk : in std_logic;
|
R_clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
W_add : in std_logic_vector(add_width -1 downto 0);
|
W_add : in std_logic_vector(add_width -1 downto 0);
|
R_add : in std_logic_vector(add_width -1 downto 0);
|
R_add : in std_logic_vector(add_width -1 downto 0);
|
Data_In : in std_logic_vector(WIDTH - 1 downto 0);
|
Data_In : in std_logic_vector(WIDTH - 1 downto 0);
|
Data_Out : out std_logic_vector(WIDTH -1 downto 0);
|
Data_Out : out std_logic_vector(WIDTH -1 downto 0);
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
COMPONENT wb_dpmem
|
COMPONENT wb_dpmem
|
GENERIC (
|
GENERIC (
|
ADD_WIDTH : INTEGER;
|
ADD_WIDTH : INTEGER;
|
WIDTH : INTEGER;
|
WIDTH : INTEGER;
|
CLK_DOMAIN : INTEGER);
|
CLK_DOMAIN : INTEGER);
|
PORT (
|
PORT (
|
CLK_I_1 : IN STD_LOGIC;
|
CLK_I_1 : IN STD_LOGIC;
|
CLK_I_2 : IN STD_LOGIC;
|
CLK_I_2 : IN STD_LOGIC;
|
ADR_I_1 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
|
ADR_I_1 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
|
ADR_I_2 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
|
ADR_I_2 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
|
DAT_O : OUT STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
|
DAT_O : OUT STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
|
DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
|
DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
|
WE_I_1 : IN STD_LOGIC;
|
WE_I_1 : IN STD_LOGIC;
|
WE_I_2 : IN STD_LOGIC;
|
WE_I_2 : IN STD_LOGIC;
|
ACK_O_1 : OUT STD_LOGIC;
|
ACK_O_1 : OUT STD_LOGIC;
|
ACK_O_2 : OUT STD_LOGIC;
|
ACK_O_2 : OUT STD_LOGIC;
|
STB_I_1 : IN STD_LOGIC;
|
STB_I_1 : IN STD_LOGIC;
|
STB_I_2 : IN STD_LOGIC);
|
STB_I_2 : IN STD_LOGIC);
|
END COMPONENT;
|
END COMPONENT;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
component Spmem_ent
|
component Spmem_ent
|
generic (
|
generic (
|
USE_RESET : boolean;
|
USE_RESET : boolean;
|
USE_CS : boolean;
|
USE_CS : boolean;
|
DEFAULT_OUT : std_logic;
|
DEFAULT_OUT : std_logic;
|
OPTION : integer;
|
OPTION : integer;
|
ADD_WIDTH : integer;
|
ADD_WIDTH : integer;
|
WIDTH : integer);
|
WIDTH : integer);
|
port (
|
port (
|
cs : std_logic;
|
cs : std_logic;
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
add : in std_logic_vector(add_width -1 downto 0);
|
add : in std_logic_vector(add_width -1 downto 0);
|
Data_In : in std_logic_vector(WIDTH -1 downto 0);
|
Data_In : in std_logic_vector(WIDTH -1 downto 0);
|
Data_Out : out std_logic_vector(WIDTH -1 downto 0);
|
Data_Out : out std_logic_vector(WIDTH -1 downto 0);
|
WR : in std_logic);
|
WR : in std_logic);
|
end component;
|
end component;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
COMPONENT WB_spmem
|
COMPONENT WB_spmem
|
GENERIC (
|
GENERIC (
|
ADD_WIDTH : INTEGER;
|
ADD_WIDTH : INTEGER;
|
WIDTH : INTEGER;
|
WIDTH : INTEGER;
|
OPTION : INTEGER);
|
OPTION : INTEGER);
|
PORT (
|
PORT (
|
DAT_O : OUT STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
|
DAT_O : OUT STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
|
DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
|
DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
|
CLK_I : IN STD_LOGIC;
|
CLK_I : IN STD_LOGIC;
|
ADR_I : IN STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
|
ADR_I : IN STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
|
STB_I : IN STD_LOGIC;
|
STB_I : IN STD_LOGIC;
|
WE_I : IN STD_LOGIC;
|
WE_I : IN STD_LOGIC;
|
ACK_O : OUT STD_LOGIC);
|
ACK_O : OUT STD_LOGIC);
|
END COMPONENT;
|
END COMPONENT;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
component FIFO_ent
|
component FIFO_ent
|
generic (
|
generic (
|
ARCH : integer;
|
ARCH : integer;
|
USE_CS : boolean;
|
USE_CS : boolean;
|
DEFAULT_OUT : std_logic;
|
DEFAULT_OUT : std_logic;
|
CLK_DOMAIN : integer;
|
CLK_DOMAIN : integer;
|
MEM_CORE : integer;
|
MEM_CORE : integer;
|
BLOCK_SIZE : integer;
|
BLOCK_SIZE : integer;
|
WIDTH : integer;
|
WIDTH : integer;
|
DEPTH : integer);
|
DEPTH : integer);
|
port (
|
port (
|
rst_n : in std_logic;
|
rst_n : in std_logic;
|
Rclk : in std_logic;
|
Rclk : in std_logic;
|
Wclk : in std_logic;
|
Wclk : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
Din : in std_logic_vector(WIDTH-1 downto 0);
|
Din : in std_logic_vector(WIDTH-1 downto 0);
|
Dout : out std_logic_vector(WIDTH-1 downto 0);
|
Dout : out std_logic_vector(WIDTH-1 downto 0);
|
Re : in std_logic;
|
Re : in std_logic;
|
wr : in std_logic;
|
wr : in std_logic;
|
UsedCount : out std_logic_vector(log2(DEPTH)-1 downto 0);
|
UsedCount : out std_logic_vector(log2(DEPTH)-1 downto 0);
|
RFull : out std_logic;
|
RFull : out std_logic;
|
RHalf_full : out std_logic;
|
RHalf_full : out std_logic;
|
REmpty : out std_logic;
|
REmpty : out std_logic;
|
WFull : out std_logic;
|
WFull : out std_logic;
|
WHalf_full : out std_logic;
|
WHalf_full : out std_logic;
|
WEmpty : out std_logic);
|
WEmpty : out std_logic);
|
end component;
|
end component;
|
|
|
end mem_pkg;
|
end mem_pkg;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|