-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Title : Single port RAM
|
-- Title : Single port RAM
|
-- Project : Memory Cores
|
-- Project : Memory Cores
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : spmem.vhd
|
-- File : spmem.vhd
|
-- Author : Jamil Khatib (khatib@ieee.org)
|
-- Author : Jamil Khatib (khatib@ieee.org)
|
-- Organization: OpenIPCore Project
|
-- Organization: OpenIPCore Project
|
-- Created : 1999/5/14
|
-- Created : 1999/5/14
|
-- Last update : 2000/12/19
|
-- Last update : 2000/12/19
|
-- Platform :
|
-- Platform :
|
-- Simulators : Modelsim 5.3XE/Windows98
|
-- Simulators : Modelsim 5.3XE/Windows98
|
-- Synthesizers: Leonardo/WindowsNT
|
-- Synthesizers: Leonardo/WindowsNT
|
-- Target :
|
-- Target :
|
-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned
|
-- Dependency : ieee.std_logic_1164,ieee.std_logic_unsigned
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description: Single Port memory
|
-- Description: Single Port memory
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Copyright (c) 2000 Jamil Khatib
|
-- Copyright (c) 2000 Jamil Khatib
|
--
|
--
|
-- This VHDL design file is an open design; you can redistribute it and/or
|
-- This VHDL design file is an open design; you can redistribute it and/or
|
-- modify it and/or implement it after contacting the author
|
-- modify it and/or implement it after contacting the author
|
-- You can check the draft license at
|
-- You can check the draft license at
|
-- http://www.opencores.org/OIPC/license.shtml
|
-- http://www.opencores.org/OIPC/license.shtml
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 1
|
-- Revision Number : 1
|
-- Version : 0.1
|
-- Version : 0.1
|
-- Date : 12 May 1999
|
-- Date : 12 May 1999
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Created
|
-- Desccription : Created
|
-- Known bugs :
|
-- Known bugs :
|
-- To Optimze :
|
-- To Optimze :
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 2
|
-- Revision Number : 2
|
-- Version : 0.2
|
-- Version : 0.2
|
-- Date : 19 Dec 2000
|
-- Date : 19 Dec 2000
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : General review
|
-- Desccription : General review
|
-- Two versions are now available with reset and without
|
-- Two versions are now available with reset and without
|
-- Default output can can be defined
|
-- Default output can can be defined
|
-- Known bugs :
|
-- Known bugs :
|
-- To Optimze :
|
-- To Optimze :
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 3
|
-- Revision Number : 3
|
-- Version : 0.3
|
-- Version : 0.3
|
-- Date : 5 Jan 2001
|
-- Date : 5 Jan 2001
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Registered Read Address feature is added to make use of
|
-- Desccription : Registered Read Address feature is added to make use of
|
-- Altera's FPGAs memory bits
|
-- Altera's FPGAs memory bits
|
-- This feature was added from Richard Herveille's
|
-- This feature was added from Richard Herveille's
|
-- contribution and his memory core
|
-- contribution and his memory core
|
-- Known bugs :
|
-- Known bugs :
|
-- To Optimze :
|
-- To Optimze :
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Single port Memory core with reset
|
-- Single port Memory core with reset
|
-- To make use of on FPGA memory bits do not use the RESET option
|
-- To make use of on FPGA memory bits do not use the RESET option
|
-- For Altera's FPGA you have to use also OPTION := 1
|
-- For Altera's FPGA you have to use also OPTION := 1
|
|
|
entity Spmem_ent is
|
entity Spmem_ent is
|
generic ( USE_RESET : boolean := false; -- use system reset
|
generic ( USE_RESET : boolean := false; -- use system reset
|
USE_CS : boolean := false; -- use chip select signal
|
USE_CS : boolean := false; -- use chip select signal
|
DEFAULT_OUT : std_logic := '1'; -- Default output
|
DEFAULT_OUT : std_logic := '1'; -- Default output
|
OPTION : integer := 1; -- 1: Registered read Address(suitable
|
OPTION : integer := 1; -- 1: Registered read Address(suitable
|
-- for Altera's FPGAs
|
-- for Altera's FPGAs
|
-- 0: non registered read address
|
-- 0: non registered read address
|
ADD_WIDTH : integer := 3;
|
ADD_WIDTH : integer := 3;
|
WIDTH : integer := 8);
|
WIDTH : integer := 8);
|
|
|
port (
|
port (
|
cs : std_logic; -- chip select
|
cs : std_logic; -- chip select
|
clk : in std_logic; -- write clock
|
clk : in std_logic; -- write clock
|
reset : in std_logic; -- System Reset
|
reset : in std_logic; -- System Reset
|
add : in std_logic_vector(add_width -1 downto 0); -- Address
|
add : in std_logic_vector(add_width -1 downto 0); -- Address
|
Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
|
Data_In : in std_logic_vector(WIDTH -1 downto 0); -- input data
|
Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
|
Data_Out : out std_logic_vector(WIDTH -1 downto 0); -- Output Data
|
WR : in std_logic); -- Read Write Enable
|
WR : in std_logic); -- Read Write Enable
|
end Spmem_ent;
|
end Spmem_ent;
|
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- This Architecture was tested on the ModelSim 5.2EE
|
-- This Architecture was tested on the ModelSim 5.2EE
|
-- The test vectors for model sim is included in vectors.do file
|
-- The test vectors for model sim is included in vectors.do file
|
|
|
|
|
architecture spmem_beh of Spmem_ent is
|
architecture spmem_beh of Spmem_ent is
|
|
|
|
|
|
|
type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
|
type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
|
-- Memory Type
|
-- Memory Type
|
signal data : data_array(0 to (2** add_width-1) ); -- Local data
|
signal data : data_array(0 to (2** add_width-1) ); -- Local data
|
|
|
|
|
-- FLEX/APEX devices require address to be registered with inclock for read operations
|
-- FLEX/APEX devices require address to be registered with inclock for read operations
|
-- This signal is used only when OPTION = 1
|
-- This signal is used only when OPTION = 1
|
signal regA : std_logic_vector( (add_width -1) downto 0);
|
signal regA : std_logic_vector( (add_width -1) downto 0);
|
|
|
procedure init_mem(signal memory_cell : inout data_array ) is
|
procedure init_mem(signal memory_cell : inout data_array ) is
|
begin
|
begin
|
|
|
for i in 0 to (2** add_width-1) loop
|
for i in 0 to (2** add_width-1) loop
|
memory_cell(i) <= (others => '0');
|
memory_cell(i) <= (others => '0');
|
end loop;
|
end loop;
|
|
|
end init_mem;
|
end init_mem;
|
|
|
begin -- spmem_beh
|
begin -- spmem_beh
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Non Registered Read Address
|
-- Non Registered Read Address
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
NON_REG : if OPTION = 0 generate
|
NON_REG : if OPTION = 0 generate
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Clocked Process with Reset
|
-- Clocked Process with Reset
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
Reset_ENABLED : if USE_RESET = true generate
|
Reset_ENABLED : if USE_RESET = true generate
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_ENABLED : if USE_CS = true generate
|
CS_ENABLED : if USE_CS = true generate
|
process (clk, reset)
|
process (clk, reset)
|
|
|
begin -- PROCESS
|
begin -- PROCESS
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
|
|
if reset = '0' then
|
if reset = '0' then
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
init_mem ( data);
|
init_mem ( data);
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
if CS = '1' then
|
if CS = '1' then
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(add));
|
data_out <= data(conv_integer(add));
|
end if;
|
end if;
|
else
|
else
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_ENABLED;
|
end generate CS_ENABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_DISABLED : if USE_CS = false generate
|
CS_DISABLED : if USE_CS = false generate
|
process (clk, reset)
|
process (clk, reset)
|
|
|
|
|
begin -- PROCESS
|
begin -- PROCESS
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
|
|
if reset = '0' then
|
if reset = '0' then
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
init_mem ( data);
|
init_mem ( data);
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(add));
|
data_out <= data(conv_integer(add));
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_DISABLED;
|
end generate CS_DISABLED;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end generate Reset_ENABLED;
|
end generate Reset_ENABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Clocked Process without Reset
|
-- Clocked Process without Reset
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
Reset_DISABLED : if USE_RESET = false generate
|
Reset_DISABLED : if USE_RESET = false generate
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_ENABLED : if USE_CS = true generate
|
CS_ENABLED : if USE_CS = true generate
|
process (clk)
|
process (clk)
|
begin -- PROCESS
|
begin -- PROCESS
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
if cs = '1' then
|
if cs = '1' then
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(add));
|
data_out <= data(conv_integer(add));
|
end if;
|
end if;
|
else
|
else
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
end if;
|
end if;
|
|
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_ENABLED;
|
end generate CS_ENABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_DISABLED : if USE_CS = false generate
|
CS_DISABLED : if USE_CS = false generate
|
process (clk)
|
process (clk)
|
begin -- PROCESS
|
begin -- PROCESS
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(add));
|
data_out <= data(conv_integer(add));
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_DISABLED;
|
end generate CS_DISABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end generate Reset_DISABLED;
|
end generate Reset_DISABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end generate NON_REG;
|
end generate NON_REG;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
REG: if OPTION = 1 generate
|
REG: if OPTION = 1 generate
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Clocked Process with Reset
|
-- Clocked Process with Reset
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
Reset_ENABLED : if USE_RESET = true generate
|
Reset_ENABLED : if USE_RESET = true generate
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_ENABLED : if USE_CS = true generate
|
CS_ENABLED : if USE_CS = true generate
|
process (clk, reset)
|
process (clk, reset)
|
|
|
begin -- PROCESS
|
begin -- PROCESS
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
|
|
if reset = '0' then
|
if reset = '0' then
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
init_mem ( data);
|
init_mem ( data);
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
regA <= add;
|
regA <= add;
|
|
|
if CS = '1' then
|
if CS = '1' then
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(regA));
|
data_out <= data(conv_integer(regA));
|
end if;
|
end if;
|
else
|
else
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_ENABLED;
|
end generate CS_ENABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_DISABLED : if USE_CS = false generate
|
CS_DISABLED : if USE_CS = false generate
|
process (clk, reset)
|
process (clk, reset)
|
|
|
|
|
begin -- PROCESS
|
begin -- PROCESS
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
|
|
if reset = '0' then
|
if reset = '0' then
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
init_mem ( data);
|
init_mem ( data);
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
regA <= add;
|
regA <= add;
|
|
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(regA));
|
data_out <= data(conv_integer(regA));
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_DISABLED;
|
end generate CS_DISABLED;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end generate Reset_ENABLED;
|
end generate Reset_ENABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Clocked Process without Reset
|
-- Clocked Process without Reset
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
Reset_DISABLED : if USE_RESET = false generate
|
Reset_DISABLED : if USE_RESET = false generate
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_ENABLED : if USE_CS = true generate
|
CS_ENABLED : if USE_CS = true generate
|
process (clk)
|
process (clk)
|
begin -- PROCESS
|
begin -- PROCESS
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
|
|
regA <= add;
|
regA <= add;
|
|
|
if cs = '1' then
|
if cs = '1' then
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(regA));
|
data_out <= data(conv_integer(regA));
|
end if;
|
end if;
|
else
|
else
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
end if;
|
end if;
|
|
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_ENABLED;
|
end generate CS_ENABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
CS_DISABLED : if USE_CS = false generate
|
CS_DISABLED : if USE_CS = false generate
|
process (clk)
|
process (clk)
|
begin -- PROCESS
|
begin -- PROCESS
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
if clk'event and clk = '1' then
|
if clk'event and clk = '1' then
|
|
|
regA <= add;
|
regA <= add;
|
|
|
if WR = '0' then
|
if WR = '0' then
|
data(conv_integer(add)) <= data_in;
|
data(conv_integer(add)) <= data_in;
|
data_out <= (others => DEFAULT_OUT);
|
data_out <= (others => DEFAULT_OUT);
|
else
|
else
|
data_out <= data(conv_integer(regA));
|
data_out <= data(conv_integer(regA));
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
end generate CS_DISABLED;
|
end generate CS_DISABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end generate Reset_DISABLED;
|
end generate Reset_DISABLED;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
end generate REG;
|
end generate REG;
|
|
|
end spmem_beh;
|
end spmem_beh;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
