-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Definitions for heap-sorter
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-- Title : Definitions for heap-sorter
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-- Project : heap-sorter
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-- Project : heap-sorter
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : sorter_pkg.vhd
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-- File : sorter_pkg.vhd
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Company :
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-- Company :
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-- Created : 2010-05-14
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-- Created : 2010-05-14
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-- Last update: 2011-07-11
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-- Last update: 2018-03-21
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-- Platform :
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-- Platform :
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 Wojciech M. Zabolotny
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-- Copyright (c) 2010 Wojciech M. Zabolotny
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-- This file is published under the BSD license, so you can freely adapt
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-- This file is published under the BSD license, so you can freely adapt
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-- it for your own purposes.
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-- it for your own purposes.
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-- Additionally this design has been described in my article:
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-- Additionally this design has been described in my article:
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-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
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-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
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-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
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-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
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-- I'd be glad if you cite this article when you publish something based
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-- I'd be glad if you cite this article when you publish something based
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-- on my design.
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-- on my design.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Date Version Author Description
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-- Date Version Author Description
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-- 2010-05-14 1.0 wzab Created
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-- 2010-05-14 1.0 wzab Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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library work;
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library work;
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use work.sys_config.all;
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use work.sys_config.all;
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package sorter_pkg is
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package sorter_pkg is
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constant DATA_REC_WIDTH : integer := DATA_REC_SORT_KEY_WIDTH +
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constant DATA_REC_WIDTH : integer := DATA_REC_SORT_KEY_WIDTH +
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DATA_REC_PAYLOAD_WIDTH + 2;
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DATA_REC_PAYLOAD_WIDTH + 2;
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subtype T_SORT_KEY is unsigned (DATA_REC_SORT_KEY_WIDTH - 1 downto 0);
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subtype T_SORT_KEY is unsigned (DATA_REC_SORT_KEY_WIDTH - 1 downto 0);
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subtype T_PAYLOAD is std_logic_vector(DATA_REC_PAYLOAD_WIDTH - 1 downto 0);
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subtype T_PAYLOAD is std_logic_vector(DATA_REC_PAYLOAD_WIDTH - 1 downto 0);
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--alias T_SORT_KEY is unsigned (12 downto 0);
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--alias T_SORT_KEY is unsigned (12 downto 0);
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type T_DATA_REC is record
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type T_DATA_REC is record
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d_key : T_SORT_KEY;
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d_key : T_SORT_KEY;
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init : std_logic;
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invalid : std_logic;
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valid : std_logic;
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d_payload : T_PAYLOAD;
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d_payload : T_PAYLOAD;
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end record;
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end record;
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-- Special constant used to initially fill the sorter
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-- Special constant used to initially fill the sorter
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-- Must be sorted so, that is smaller, than any other data
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-- Must be sorted so, that is smaller, than any other data
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constant DATA_REC_INIT_DATA : T_DATA_REC := (
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constant DATA_REC_INIT_DATA : T_DATA_REC := (
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d_key => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
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d_key => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
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init => '1',
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invalid => '1',
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valid => '0',
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d_payload => (others => '0')
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d_payload => (others => '0')
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);
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);
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-- Special constant used to ``flush'' the sorter at the end
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-- Special constant used to ``flush'' the sorter at the end
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constant DATA_REC_END_DATA : T_DATA_REC := (
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constant DATA_REC_END_DATA : T_DATA_REC := (
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d_key => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
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d_key => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
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init => '1',
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invalid => '1',
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valid => '1',
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d_payload => (others => '0')
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d_payload => (others => '0')
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);
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);
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function sort_cmp_lt (
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function sort_cmp_lt (
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constant v1 : T_DATA_REC;
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constant v1 : T_DATA_REC;
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constant v2 : T_DATA_REC)
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constant v2 : T_DATA_REC)
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return boolean;
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return boolean;
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function tdrec2stlv (
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function tdrec2stlv (
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constant drec : T_DATA_REC)
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constant drec : T_DATA_REC)
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return std_logic_vector;
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return std_logic_vector;
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function stlv2tdrec (
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function stlv2tdrec (
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constant dstlv : std_logic_vector)
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constant dstlv : std_logic_vector)
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return T_DATA_REC;
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return T_DATA_REC;
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procedure wrstlv (
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procedure wrstlv (
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rline : inout line;
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rline : inout line;
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constant vect : std_logic_vector);
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constant vect : std_logic_vector);
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file reports : text open write_mode is "STD_OUTPUT";
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file reports : text open write_mode is "STD_OUTPUT";
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end sorter_pkg;
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end sorter_pkg;
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package body sorter_pkg is
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package body sorter_pkg is
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function stlv2tdrec (
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function stlv2tdrec (
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constant dstlv : std_logic_vector)
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constant dstlv : std_logic_vector)
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return T_DATA_REC is
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return T_DATA_REC is
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variable result : T_DATA_REC;
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variable result : T_DATA_REC;
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variable j : integer := 0;
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variable j : integer := 0;
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begin -- stlv2drec
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begin -- stlv2drec
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j := 0;
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j := 0;
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result.d_key := unsigned(dstlv(j-1+DATA_REC_SORT_KEY_WIDTH downto j));
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result.d_key := unsigned(dstlv(j-1+DATA_REC_SORT_KEY_WIDTH downto j));
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j := j+DATA_REC_SORT_KEY_WIDTH;
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j := j+DATA_REC_SORT_KEY_WIDTH;
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result.valid := dstlv(j);
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result.invalid := dstlv(j);
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j := j+1;
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result.init := dstlv(j);
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j := j+1;
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j := j+1;
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result.d_payload := dstlv(j-1+DATA_REC_PAYLOAD_WIDTH downto j);
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result.d_payload := dstlv(j-1+DATA_REC_PAYLOAD_WIDTH downto j);
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j := j+DATA_REC_PAYLOAD_WIDTH;
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j := j+DATA_REC_PAYLOAD_WIDTH;
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return result;
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return result;
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end stlv2tdrec;
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end stlv2tdrec;
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function tdrec2stlv (
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function tdrec2stlv (
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constant drec : T_DATA_REC)
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constant drec : T_DATA_REC)
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return std_logic_vector is
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return std_logic_vector is
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variable result : std_logic_vector(DATA_REC_WIDTH-1 downto 0);
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variable result : std_logic_vector(DATA_REC_WIDTH-1 downto 0);
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variable j : integer := 0;
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variable j : integer := 0;
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begin -- tdrec2stlv
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begin -- tdrec2stlv
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j := 0;
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j := 0;
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result(j-1+DATA_REC_SORT_KEY_WIDTH downto j) := std_logic_vector(drec.d_key);
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result(j-1+DATA_REC_SORT_KEY_WIDTH downto j) := std_logic_vector(drec.d_key);
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j := j+DATA_REC_SORT_KEY_WIDTH;
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j := j+DATA_REC_SORT_KEY_WIDTH;
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result(j) := drec.valid;
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result(j) := drec.invalid;
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j := j+1;
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result(j) := drec.init;
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j := j+1;
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j := j+1;
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result(j-1+DATA_REC_PAYLOAD_WIDTH downto j) := std_logic_vector(drec.d_payload);
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result(j-1+DATA_REC_PAYLOAD_WIDTH downto j) := std_logic_vector(drec.d_payload);
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j := j+DATA_REC_PAYLOAD_WIDTH;
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j := j+DATA_REC_PAYLOAD_WIDTH;
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return result;
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return result;
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end tdrec2stlv;
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end tdrec2stlv;
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-- Function sort_cmp_lt returns TRUE when the first opperand is ``less'' than
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-- Function sort_cmp_lt returns TRUE when the first opperand is ``less'' than
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-- the second one
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-- the second one
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function sort_cmp_lt (
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function sort_cmp_lt (
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constant v1 : T_DATA_REC;
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constant v1 : T_DATA_REC;
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constant v2 : T_DATA_REC)
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constant v2 : T_DATA_REC)
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return boolean is
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return boolean is
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variable rline : line;
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variable rline : line;
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variable dcomp : unsigned(DATA_REC_SORT_KEY_WIDTH-1 downto 0) := (others => '0');
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variable dcomp, key1, key2 : unsigned(DATA_REC_SORT_KEY_WIDTH downto 0) := (others => '0');
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begin -- sort_cmp_lt
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begin -- sort_cmp_lt
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-- Check the special cases
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if (v1.init = '1') and (v2.init = '0') then
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-- v1 is the special record, v2 is the standard one
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if v1.valid = '0' then
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-- initialization record - ``smaller'' than all standard records
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return true;
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else
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-- end record - ``bigger'' than all standard records
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return false;
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end if;
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elsif (v1.init = '0') and (v2.init = '1') then
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-- v2 is the special record, v1 is the standard one
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if (v2.valid = '0') then
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-- v2 is the initialization record - it is ``smaller'' than standard record v1
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return false;
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else
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-- v2 is the end record - it is ``bigger'' than standard record v1
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return true;
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end if;
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elsif (v1.init = '1') and (v2.init = '1') then
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-- both v1 and v2 are special records
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if (v1.valid = '0') and (v2.valid = '1') then
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-- v1 - initial record, v2 - end record
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return true;
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else
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-- v1 is end record, so it is ``bigger'' or ``equal'' to other records
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return false;
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end if;
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elsif (v1.init = '0') and (v2.init = '0') then
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-- We compare standard words
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-- We compare standard words
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-- We must consider the fact, that in longer sequences of data records
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-- We must consider the fact, that in longer sequences of data records
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-- the sort keys may wrap around
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-- the sort keys may wrap around
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-- therefore we perform subtraction modulo
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-- therefore we perform subtraction modulo
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-- 2**DATA_REC_SORT_KEY_WIDTH and check the MSB
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-- 2**DATA_REC_SORT_KEY_WIDTH and check the MSB
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dcomp := v1.d_key-v2.d_key;
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key1 := v1.d_key & v1.invalid;
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if dcomp(DATA_REC_SORT_KEY_WIDTH-1) = '1' then
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key2 := v2.d_key & v2.invalid;
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dcomp := key1-key2;
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if dcomp(DATA_REC_SORT_KEY_WIDTH) = '1' then
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--if signed(v1.d_key - v2.d_key)<0 then -- old implementation
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--if signed(v1.d_key - v2.d_key)<0 then -- old implementation
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return true;
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return true;
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elsif v2.d_key = v1.d_key then
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if v2.valid = '1' then
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return true;
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else
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-- Empty data records should wait
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return false;
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end if;
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else
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return false;
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end if;
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else
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else
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assert false report "Wrong records in sort_cmp_lt" severity error;
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return false;
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return false;
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end if;
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end if;
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return false; -- should never happen
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return false; -- should never happen
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end sort_cmp_lt;
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end sort_cmp_lt;
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procedure wrstlv (
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procedure wrstlv (
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rline : inout line;
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rline : inout line;
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constant vect : std_logic_vector) is
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constant vect : std_logic_vector) is
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begin -- stlv2str
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begin -- stlv2str
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for i in vect'left downto vect'right loop
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for i in vect'left downto vect'right loop
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case vect(i) is
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case vect(i) is
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when 'U' => write(rline, string'("u"));
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when 'U' => write(rline, string'("u"));
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when 'Z' => write(rline, string'("z"));
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when 'Z' => write(rline, string'("z"));
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when 'X' => write(rline, string'("x"));
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when 'X' => write(rline, string'("x"));
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when 'L' => write(rline, string'("L"));
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when 'L' => write(rline, string'("L"));
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when 'H' => write(rline, string'("H"));
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when 'H' => write(rline, string'("H"));
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when '1' => write(rline, string'("1"));
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when '1' => write(rline, string'("1"));
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when '0' => write(rline, string'("0"));
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when '0' => write(rline, string'("0"));
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when others => write(rline, string'("?"));
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when others => write(rline, string'("?"));
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end case;
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end case;
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end loop; -- i
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end loop; -- i
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end wrstlv;
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end wrstlv;
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end sorter_pkg;
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end sorter_pkg;
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