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-- A parameterized, inferable, true dual-port, common-clock block RAM in VHDL.
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-- Original file was taken from: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
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-- No license information were provided by the original author.
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-- Minimal modifications were introduced by me to make it suitable for my sorter.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity dp_ram_scl is
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generic (
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DATA_WIDTH : integer := 72;
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ADDR_WIDTH : integer := 10
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);
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port (
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-- common clock
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clk : in std_logic;
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-- Port A
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we_a : in std_logic;
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addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
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data_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
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q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
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-- Port B
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we_b : in std_logic;
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addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
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data_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
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q_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end dp_ram_scl;
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architecture rtl of dp_ram_scl is
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-- Shared memory
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type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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shared variable mem : mem_type;
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begin
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-- Port A
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process(clk)
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begin
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if(clk'event and clk = '1') then
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if(we_a = '1') then
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mem(conv_integer(addr_a)) := data_a;
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end if;
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q_a <= mem(conv_integer(addr_a));
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end if;
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end process;
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-- Port B
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process(clk)
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begin
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if(clk'event and clk = '1') then
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if(we_b = '1') then
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mem(conv_integer(addr_b)) := data_b;
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end if;
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q_b <= mem(conv_integer(addr_b));
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end if;
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end process;
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end rtl;
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